Heterogeneous Conductive Line Layout for Sub-15 Nm Overlay Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling integrated circuit features to sub-15 nanometer nodes due to variability in conventional fabrication processes, which limits the extension of technology nodes and requires new methodologies or integration of new technologies to optimize performance.
Innovation Solution
The implementation of differentiated conductive line approaches, including the use of Co, Ru, W, or Mo for initial metallization, followed by patterning and backfilling with Cu, and the application of pitch quartering and halving schemes to enable finer feature sizes and improved overlay control, along with the use of heterogeneous metallization layers for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-15 nanometer nodes
Solution Approach 1:
The fabrication process is divided into multiple distinct stages: initial metallization with Co/Ru/W/Mo, patterning to create trenches, and backfilling with Cu. This segmentation allows each stage to be optimized independently for precision while managing overall process complexity.
Solution Approach 2:
Different metal compositions are used for different line widths within the same metallization layer. Narrow lines use one composition while wide lines use another, allowing local optimization of electrical performance and manufacturing precision for each line type.
2Reliability
If single metal composition is used for all conductive lines, then manufacturing simplicity is maintained, but performance deteriorates due to inability to optimize for different line widths
Solution Approach 1:
The patent implements heterogeneous metallization where narrow conductive lines use one metal composition (e.g., Co, Ru, W, or Mo) and wide conductive lines use another (e.g., Cu). This local differentiation allows each line type to be optimized for its specific electrical performance requirements while managing overall structure complexity.
Solution Approach 2:
The metallization layer becomes a composite structure containing multiple metal compositions within the same layer. This composite approach enables the system to achieve the performance benefits of different materials (low resistivity, electromigration resistance) in different locations without requiring separate layers for each function.
3Manufacturing precision
If pitch quartering and halving schemes are applied, then manufacturing precision is improved for overlay control, but device complexity increases
Solution Approach 1:
The patterning process is segmented into multiple steps including pitch quartering and halving schemes. Each segmentation step reduces the feature size by a factor, allowing precise control of overlay tolerances while breaking down the complex patterning task into manageable stages.
Data Source
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AI summary
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The integrated circuit structure also includes an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines.