Heterogeneous Memory Management via Logical Distance Affinity

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Solution Overview

Problem

Computer systems face inefficiencies when using a single type of memory, as newer non-volatile memory technologies like NAND flash become cost-effective but demonstrate poorer performance than DRAM, necessitating a balance between price, speed, and power dissipation, while existing methods fail to effectively manage heterogeneous memory types for optimal performance.

Innovation Solution

Implementing a method that uses a controller hub to manage heterogeneous memory types by creating an affinity table that assigns logical distances to each memory type based on access times, allowing the operating system to schedule operations and allocate resources efficiently across different memory types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If non-volatile memory (NVM) such as flash devices is used to reduce cost, then cost is improved, but performance deteriorates

Engineering Contradiction:
ImprovecostVSAvoidperformance
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent combines multiple memory types (DRAM and NVM) into a single heterogeneous memory system, allowing the system to leverage both the low cost of NVM and the high performance of DRAM simultaneously. The memory controller manages both memory types together, creating a unified memory architecture that achieves cost reduction without complete performance sacrifice.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies different memory types to different operational requirements within the same system. Fast DRAM is used for time-critical operations while slower NVM handles less time-sensitive tasks, allowing each memory type to operate in its optimal performance zone and achieving overall system efficiency.

Inventive Principle:
Principle #3Local quality

2Speed

If DRAM is used for high speed performance, then speed is improved, but cost increases

Engineering Contradiction:
ImprovespeedVSAvoidcost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

Instead of using DRAM for all memory operations, the patent applies DRAM only partially - specifically for time-critical operations that require high speed. Less time-sensitive operations use the cheaper NVM, thereby reducing overall cost while maintaining necessary performance levels.

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If multiple memory types are mixed to balance cost and performance, then cost-effectiveness is improved, but system complexity increases

Engineering Contradiction:
Improvecost-effectivenessVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a memory controller as an intermediary that manages the complexity of heterogeneous memory types. The controller handles the differences between DRAM and NVM characteristics, translating high-level memory operations into appropriate physical memory actions, thereby shielding the rest of the system from complexity while enabling cost-effective mixed memory usage.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If affinity tables are used to manage heterogeneous memory, then memory allocation efficiency is improved, but device complexity increases

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses affinity tables that store and manipulate parameters describing memory characteristics (such as speed, cost, and accessibility). By changing and optimizing these parameters dynamically, the system achieves efficient memory allocation across heterogeneous types without requiring complex hardwired control logic.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7685376B2Method to support heterogeneous memories
Publication Date: 2010.03.23 INTEL CORP
  • US7685376B2 patent drawing
  • US7685376B2 patent drawing
  • US7685376B2 patent drawing

AI summary

A method and apparatus is described herein for supporting heterogeneous local memories. A resource affinity table includes an entry for each local memory mapped into an address space. Each entry associating the corresponding local memory with a logical distance, such as a domain number. During runtime thread scheduling, memory operations, and other tasks are potentially assigned to the local memory devices based on the logical distance associated with each memory in the resource affinity table. As a consequence, heterogeneous memory types or homogeneous memories with different access times may be efficiently combined in a system to achieve large amount of memory at a smaller cost without sacrificing performance by allowing an operating system to make intelligent scheduling choices based on logical distances/access times of the aforementioned memories.