Heterogeneous Memory Interleaving for Unified Bandwidth Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing systems face challenges in efficiently utilizing the full memory bandwidth of heterogeneous memory targets due to tiered memory approaches that separate memory types into distinct address spaces, limiting applications from exploiting the combined bandwidth and placing a burden on OS/VMM scheduling.
Innovation Solution
Interleaving heterogeneous memory targets, such as DDR5 and CXL, into a single continuous software-visible address range, allowing applications to access the full memory bandwidth and simplifying OS/VMM scheduling by uniformly scheduling applications across the interleaved memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tiered memory approaches separate memory types into distinct address spaces, then memory management is simplified, but applications cannot exploit the combined bandwidth of heterogeneous memory targets
Solution Approach 1:
The patent merges heterogeneous memory targets (DDR5, CXL, HBM) into a single unified address space, allowing applications to access all memory types through continuous address ranges. This combining approach enables full bandwidth exploitation by eliminating the fragmentation caused by separate address spaces while maintaining manageable configuration through systematic address allocation.
Solution Approach 2:
The unified address space serves multiple functions simultaneously: it provides a common access interface for all applications, enables bandwidth aggregation across heterogeneous memory types, and maintains compatibility with existing memory management mechanisms. This universal address space acts as a multi-functional layer that reconciles the need for both simplicity and performance.
2Ease of operation
If tiered memory approaches are used, then memory targets of the same type can be managed uniformly, but OS/VMM scheduling becomes burdened with complex scheduling decisions
Solution Approach 1:
The unified address space acts as an intermediary layer between applications and heterogeneous memory targets. Instead of requiring the OS/VMM to make complex scheduling decisions about which memory type to use, the unified address space automatically routes memory accesses to appropriate memory targets based on address patterns, thereby simplifying OS/VMM scheduling while maintaining uniform management capabilities.
3Productivity
If separate address ranges are configured for different memory types, then memory targets can be individually accessed, but memory accesses are not evenly distributed across targets
Solution Approach 1:
The unified address space is segmented into sub-ranges that map to different heterogeneous memory targets. This segmentation strategy ensures that memory accesses are evenly distributed across all available memory targets by allocating specific address ranges to specific memory types, thereby maximizing throughput while maintaining simple access patterns for applications.
Data Source
AI summary
An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.