Unified Processor and Heterogeneous Memory Stack for Lower RC Delay
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Solution Overview
Problem
Conventional semiconductor devices face challenges with cross-talk and high loading on processors due to the use of homogeneous memory types and long-distance metal wires, leading to RC delay and increased PCB area, which affects data storage performance and efficiency.
Innovation Solution
A unified semiconductor device with a processor core and heterogeneous memories (DRAM and NAND) integrated in a multi-chip package or on the same bonded chip, utilizing short-distance vertical metal interconnects and reducing or eliminating bus interface units to enhance data storage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If homogeneous memory types and long-distance metal wires are used, then device complexity is reduced, but RC delay increases and data storage performance deteriorates
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to three-dimensional (3D) stacked architecture, where memory layers are stacked vertically above the processor. This dimensional change enables short-distance vertical interconnects through the substrate, dramatically reducing RC delay while maintaining heterogeneous memory integration.
Solution Approach 2:
The patent segments different types of memory (DRAM, NAND, SRAM) into separate stacked layers, each optimized for specific functions. This segmentation allows heterogeneous memory types to be integrated without increasing overall device complexity, as each layer operates independently with dedicated interconnects.
2Quantity of substance
If heterogeneous memories are integrated in multi-chip package, then data storage capacity increases, but device complexity increases
Solution Approach 1:
The patent merges processor and heterogeneous memory into a single integrated device structure, eliminating the need for separate multi-chip packages. The processor and memory layers are bonded together in a unified stack, increasing data storage capacity while reducing package-level complexity through monolithic integration.
Solution Approach 2:
The integrated device structure serves multiple functions simultaneously: the processor handles computation while stacked memory layers provide various types of storage (volatile DRAM, non-volatile NAND, cache SRAM). This multi-functionality eliminates the need for separate chips and packages, reducing overall device complexity.
3Manufacturing precision
If long-distance metal wires are used, then manufacturing precision requirements are reduced, but RC delay increases and processor loading increases
Solution Approach 1:
The patent replaces long-distance lateral wire connections with short-distance vertical interconnects through the substrate. This dimensional change in signal routing dramatically reduces RC delay while the standardized vertical interconnect structure simplifies manufacturing precision requirements compared to complex lateral routing.
4Productivity
If bus interface units are eliminated, then processor loading is reduced, but device complexity increases due to direct integration
Solution Approach 1:
The patent merges the functions previously performed by separate bus interface units directly into the processor and memory layers. Data transfer occurs through direct vertical interconnects between stacked layers, eliminating the need for intermediate bus interface units and reducing processor loading while simplifying the overall integration structure.
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.