Heterogeneous Memory Cache Management for Miss Penalty Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In data processing systems, the presence of multiple memory devices with different characteristics leads to access errors and increased miss penalties due to cache management inefficiencies, particularly in high-capacity memory systems used in mobile communication terminals and data centers.

Innovation Solution

A data processing system that includes a compute blade for generating commands and a memory blade for performing read/write operations, utilizing a cache memory to determine priority information for eviction based on stored performance characteristics of each memory device, and a host that profiles memory access patterns to predict data access and transmit subset data, reducing overhead and miss penalties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory devices with different characteristics are used to increase storage capacity, then storage capacity is improved, but access errors and miss penalties increase due to cache management inefficiencies

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory system is segmented into multiple memory devices (first memory device, second memory device, etc.) with different characteristics. Each memory device can be independently managed with customized cache management policies, allowing the system to handle diverse memory types (e.g., fast but small, slow but large) without interference, thus maintaining access accuracy while increasing total storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache management policy is made dynamic and adaptable to different memory device characteristics. The system can dynamically select appropriate cache management strategies for each memory device based on its specific properties (speed, capacity, access patterns), enabling efficient utilization of heterogeneous memory resources while minimizing access errors and miss penalties.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If multiple memory devices with different characteristics are used to increase storage capacity, then storage capacity is improved, but miss penalties increase due to cache management inefficiencies

Engineering Contradiction:
Improvestorage capacityVSAvoidmiss penalty
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

Different cache management policies are applied locally to different memory devices based on their specific characteristics. For example, faster memory devices may use more aggressive caching strategies while slower devices use more conservative approaches. This localized optimization reduces overall miss penalties by ensuring each memory device operates at its optimal performance level.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system implements feedback mechanisms to monitor cache performance and access patterns across multiple memory devices. Based on this feedback, the cache management policies are continuously optimized to minimize miss penalties. The system learns from actual performance data and adjusts caching strategies to prevent future misses, thereby reducing time loss.

Inventive Principle:
Principle #23Feedback

3Device complexity

If traditional cache management is used without considering memory characteristics, then system simplicity is maintained, but access errors and performance degradation occur

Engineering Contradiction:
Improvecache management complexityVSAvoidaccess accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The cache management system is segmented into device-specific management modules, where each memory device has its own customized cache management policy. This segmentation allows the system to maintain simplicity at the individual device level while achieving high reliability through specialized handling of each memory device's unique characteristics.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240338215A1Memory system and data processing system including the same
Publication Date: 2024.10.10 SK HYNIX INC
  • US20240338215A1 patent drawing
  • US20240338215A1 patent drawing
  • US20240338215A1 patent drawing

AI summary

A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.