3D Heterogeneous Memory Stacking for Density Without Finer Scaling
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Solution Overview
Problem
The existing planar memory cell technology faces challenges in scaling due to limitations in feature size, leading to a ceiling in memory density and increased manufacturing costs.
Innovation Solution
A 3D memory device architecture is proposed, which stacks heterogeneous memories such as NAND, DRAM, and SRAM, using face-to-face bonding with hybrid bonding interfaces to reduce interlayer electrical connections and enhance manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing cost increases and feature size approaches lower limit
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple memory dies of different types (NAND, DRAM, SRAM) are vertically stacked and bonded together, utilizing the third dimension to increase memory density without further reducing feature sizes in the planar direction. This dimensional transition allows continued scaling of memory capacity while maintaining manufacturable feature sizes.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but process and fabrication techniques become challenging
Solution Approach 1:
The patent divides the memory system into multiple separate memory dies (NAND die, DRAM die, SRAM die) that are fabricated independently using their respective optimized processes. Each die type can be manufactured with its own specialized fabrication techniques without interfering with others. These segmented dies are then bonded together through wafer-level or chip-level packaging, transferring the integration challenge from fabrication to assembly where precision requirements are more manageable.
3Quantity of substance
If heterogeneous memory types are integrated in 3D stack, then memory density and data transfer rate are improved, but device complexity increases
Solution Approach 1:
The patent creates a universal 3D stacked memory architecture that can accommodate multiple memory types (NAND, DRAM, SRAM) with different characteristics and use cases. The bonding interface and interconnect structure are designed to be type-agnostic, allowing different memory dies to be stacked in various configurations depending on performance requirements. This multi-functional platform reduces integration complexity by providing a standardized approach that works across different memory technologies.
Data Source
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AI summary
Embodiments of three-dimensional (3D) memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes NAND memory cells and a first bonding layer including first bonding contacts. The 3D memory device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The 3D memory device also includes a third semiconductor structure including SRAM cells, a third bonding layer including third bonding contacts, and a fourth bonding layer including fourth bonding contacts. The third and fourth bonding layers are on both sides of the SRAM cells. The semiconductor device further includes a first bonding interface between the first and third bonding layers. The first bonding contacts are in contact with the third bonding contacts at the first bonding interface. The 3D memory device further includes a second bonding interface between the second and fourth bonding layers. The second bonding contacts are in contact with the fourth bonding contacts at the second bonding interface.