Heterogeneous Memory System with NVRAM and DRAM

The patent combines DRAM and NVRAM into a single memory device package, creating a hybrid memory system that provides both high-speed volatile storage and high-capacity non-volatile storage in one compact unit. This merging allows the system to achieve increased storage capacity without proportionally increasing system volume, as the NVRAM layer can be stacked over or integrated with the DRAM layer in a three-dimensional architecture.

The patent implements a nested memory hierarchy where NVRAM is positioned as a underlying layer beneath DRAM within the same memory device. This nesting arrangement allows the DRAM to provide fast access for active data while the NVRAM provides high-capacity storage for less frequently accessed data, effectively increasing total memory capacity within the same physical footprint without requiring additional system volume.

The patent applies local quality by assigning different memory types to different functional requirements within the same memory system. DRAM is used locally for storing frequently accessed data requiring high speed, while NVRAM is used locally for storing less frequently accessed data where power consumption is more critical. This localized assignment allows the system to optimize power consumption by accessing NVRAM for cold data without sacrificing the high-speed performance needed for hot data in DRAM.

The patent implements a dynamic memory management system that can adaptively move data between DRAM and NVRAM layers based on access patterns and power state. When the system enters low-power mode, frequently accessed data can be pre-loaded into DRAM while less critical data resides in NVRAM, allowing the system to reduce power consumption by maintaining only essential data in the power-hungry DRAM layer while preserving fast access capability when needed.

The patent implements preliminary action by pre-loading frequently accessed data from NVRAM into DRAM before it is needed for processing. The memory controller monitors access patterns and proactively transfers data that is likely to be accessed soon from the slower NVRAM layer to the faster DRAM layer, thereby reducing the effective access latency for hot data while maintaining the power-saving benefits of using NVRAM for the bulk storage capacity.

The patent introduces a memory controller as an intermediary between the processor and the heterogeneous memory layers. This intermediary intelligently manages data transfer between DRAM and NVRAM, caching frequently accessed data in DRAM and managing the access hierarchy to minimize latency. The memory controller acts as a mediator that transparently handles the latency difference between the two memory types by optimizing data placement and access paths, allowing the system to use power-efficient NVRAM without experiencing its full latency penalty.