Heterogeneous Memory Power Optimization

Solution Overview

Problem

The increasing power consumption of dynamic random access memory (DRAM) in portable computing devices due to higher density and speed requirements poses a significant challenge, as DRAM requires frequent refresh operations to maintain data integrity, leading to higher energy usage.

Innovation Solution

A heterogeneous system memory configuration is implemented, combining nonvolatile random access memory (NVRAM) and volatile random access memory (VRAM) within a system on chip (SoC), where NVRAM is used for read-only operations and data retention, and VRAM for program heaps and stacks, with a memory manager optimizing allocation based on write and read counts to reduce overall power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If DRAM density and speed requirements are increased, then memory performance is improved, but power consumption increases

Engineering Contradiction:

Improvememory speedVSAvoidmemory power consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The memory system is segmented into two distinct types: volatile memory (DRAM) for high-speed temporary storage and non-volatile memory (NVRAM) for persistent storage. This segmentation allows each memory type to operate in its optimal performance range while consuming less overall power, as NVRAM does not require continuous refresh operations like DRAM

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the physical state parameters of memory by using NVRAM that maintains data without power (non-volatile) compared to DRAM that requires continuous power and refresh operations. This parameter change eliminates the need for frequent refresh operations, directly reducing power consumption while maintaining adequate performance

Inventive Principle:

Principle #35Parameter changes

2Reliability

If DRAM refresh operations are performed frequently, then data integrity is maintained, but energy usage increases

Engineering Contradiction:

Improvedata integrityVSAvoidenergy usage

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory system is segmented into two distinct types: volatile memory (DRAM) for high-speed temporary storage and non-volatile memory (NVRAM) for persistent storage. This segmentation allows each memory type to operate in its optimal performance range while consuming less overall power, as NVRAM does not require continuous refresh operations like DRAM

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the physical state parameters of memory by using NVRAM that maintains data without power (non-volatile) compared to DRAM that requires continuous power and refresh operations. This parameter change eliminates the need for frequent refresh operations, directly reducing power consumption while maintaining adequate performance

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP3289465B1Systems and methods for optimizing memory power consumption in a heterogeneous system memory

Publication Date: 2022.11.02 QUALCOMM INC

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AI summary

Systems, methods, and computer programs are disclosed for providing a heterogeneous system memory in a portable communication device. One system comprises a system on chip (SoC) coupled to a nonvolatile random access memory (NVRAM) and a volatile random access memory (VRAM). The SoC comprises an operating system for mapping a heterogeneous system memory comprising the NVRAM and the VRAM. The operating system comprises a memory manager configured to allocate a first portion of the NVRAM as a block device for a swap operation, a second portion of the NVRAM for program code and read-only data, and a third portion of the NVRAM for operating system page tables. The VRAM is allocated for a program heap and a program stack.