Heterogeneous Memory System Routing for Power and Speed Tradeoffs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Processor-based systems face challenges in optimizing memory access requests due to the tradeoff between power consumption and performance, as they typically rely on either volatile or non-volatile memory, which have different characteristics that cannot be efficiently managed with a single memory type.
Innovation Solution
A heterogeneous memory system is introduced, comprising multiple homogeneous memories with different power and performance characteristics, where memory access requests are routed based on predefined or dynamically determined policies considering factors like read/write type, frequency of page hits, and memory traffic, using a bus interconnect arbiter to optimize access times without requiring architecture changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is used, then performance (read/write speeds) is improved, but power consumption increases due to refreshing requirements
Solution Approach 1:
The memory system is segmented into multiple independent memory types (volatile and non-volatile), each handling different workloads. The volatile memory segment handles performance-critical operations while the non-volatile segment handles less time-sensitive operations, allowing the system to achieve both high speed and low power consumption for different memory access patterns simultaneously.
Solution Approach 2:
The system dynamically selects which memory type to use for each memory access request based on real-time conditions such as workload characteristics, power availability, and performance requirements. This dynamic allocation allows the system to optimize the trade-off between speed and power consumption adaptively rather than being fixed to a single memory type.
2Use of energy by moving object
If non-volatile memory is used, then power consumption is reduced, but performance (read/write speeds) deteriorates
Solution Approach 1:
Different memory types are assigned to different functional requirements within the system. Non-volatile memory is used locally for operations where power savings are critical and performance requirements are less stringent, while volatile memory is used locally for operations requiring high speed. This local quality differentiation allows each memory type to operate in its optimal performance regime.
3Device complexity
If a single memory type is used, then system complexity is reduced, but adaptability to different power and performance requirements deteriorates
Solution Approach 1:
The memory system is designed with multi-functionality by incorporating multiple memory types that can serve different purposes within the same system architecture. The bus interconnect arbiter provides a universal interface that can route requests to either volatile or non-volatile memory based on requirements, making the system adaptable to various power and performance scenarios without requiring separate specialized systems.
Solution Approach 2:
The bus interconnect arbiter acts as an intermediary between the processor and the heterogeneous memory system. It transparently manages the complexity of routing memory requests to appropriate memory types based on policies considering power and performance requirements, thereby hiding the system complexity from the processor while providing adaptability.
Data Source
AI summary
Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.