Heterogeneous Memory Controller Ready Signal Mechanism
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Solution Overview
Problem
Non-volatile dual-inline memory modules (NVDIMM-P) with persistent storage introduce non-deterministic access latencies, requiring a handshake protocol to manage data availability, which can delay memory access and impact performance.
Innovation Solution
A memory controller with a heterogeneous memory channel interface, non-volatile command queue, arbiter, and control circuit is used to manage memory access commands, including volatile and non-volatile reads/writes, allowing for efficient transmission and handling of non-volatile read commands through a heterogenous memory channel, reducing delays by utilizing a ready response to initiate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a handshake protocol is used to manage data availability from NVDIMM-P, then data access reliability is improved, but memory access speed deteriorates due to temporary delays
Solution Approach 1:
The patent implements a preliminary action by using a ready signal mechanism where the NVDIMM-P proactively notifies the memory controller when data is available in the buffer, rather than waiting for the controller to poll or wait for confirmation. This advance notification allows the controller to prepare for data reception immediately, reducing waiting time while maintaining reliable data transfer.
Solution Approach 2:
The patent employs feedback through a ready signal that flows from the NVDIMM-P to the memory controller, creating a closed-loop communication system. This feedback mechanism allows the controller to adjust its operation based on the actual data availability status, enabling efficient handshaking that maintains reliability without unnecessary delays.
2Measurement precision
If non-volatile read commands are held in the memory interface queue to manage non-deterministic latency, then data access accuracy is improved, but processing efficiency deteriorates due to increased queue holding time
Solution Approach 1:
The patent uses preliminary action by pre-queuing non-volatile read commands in the memory interface queue before data is actually ready. This allows the controller to prepare and organize commands in advance, so when data becomes available (indicated by the ready signal), the corresponding commands are already positioned for immediate execution, reducing the actual waiting time and improving processing efficiency while maintaining accurate command-data matching.
Data Source
AI summary
A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.