Heterogeneous Memory Storage Capacity via Resistance Segmentation
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Solution Overview
Problem
Heterogeneous storage elements in memory systems, such as phase change memory (PCM), face challenges in storing and retrieving data due to varying physical characteristics among cells, leading to errors and reduced storage capacity in existing approaches that assume binary states or common resistance ranges.
Innovation Solution
The method involves determining the physical characteristics of memory cells, generating constraint vectors, and calculating virtual write vectors to write data bit-by-bit, skipping stuck locations, thereby optimizing data storage across cells with different resistance levels, and using coding techniques to ensure compatibility with cell resistance ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common range of resistance values is used across all memory elements, then errors are reduced, but storage capacity is lost
Solution Approach 1:
The memory array is divided into multiple segments or groups, where each segment is assigned a specific resistance range based on the capabilities of its memory elements. This segmentation allows different segments to utilize different portions of the resistance spectrum, thereby increasing overall storage capacity while maintaining reliability within each segment's designated range.
Solution Approach 2:
Different resistance ranges are assigned to different spatial locations or groups of memory elements based on their individual characteristics. This local optimization allows each memory element to operate within its optimal resistance range, maximizing the usable storage capacity of the entire array while ensuring reliable operation locally.
2Reliability
If memory elements are treated as binary (defective or non-defective), then defective elements are circumvented, but heterogeneity is not fully utilized
Solution Approach 1:
Instead of treating memory elements as binary (defective/non-defective), the system utilizes multiple resistance levels within a defined range for each element. By changing from a binary state to a multi-level state, the system can accommodate heterogeneity while fully utilizing the resistance characteristics of each memory element, thereby improving both reliability and adaptability.
Solution Approach 2:
The system dynamically assigns resistance ranges to memory elements based on their measured characteristics rather than using fixed binary classification. This dynamic adaptation allows the system to optimize the use of each element's specific resistance profile, fully leveraging heterogeneity while maintaining reliable operation.
3Quantity of substance
If the full range of resistance levels in each cell is utilized, then storage capacity increases, but errors may increase due to heterogeneity
Solution Approach 1:
The system performs preliminary characterization of each memory element's resistance range before data storage. By measuring and determining the optimal resistance range for each element in advance, the system can then assign data to appropriate resistance levels within that range, thereby maximizing storage capacity while avoiding errors that would result from using inappropriate resistance values.
Solution Approach 2:
The system incorporates feedback mechanisms to monitor and adjust the resistance levels used for data storage. By continuously monitoring the performance and error rates of memory elements, the system can dynamically adjust the resistance ranges assigned to different elements or segments, thereby maintaining low error rates while utilizing the full storage capacity of each element.
Data Source
AI summary
Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.