Heterogeneous Memory Stack Layout for Density and Channel Control
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in the fabrication of tri-gate transistors on bulk silicon substrates, is exacerbated by the need for improved semiconductor structures and fabrication techniques in integrated circuits.
Innovation Solution
A vertically stacked arrangement of heterogeneous memory arrays is implemented, comprising active layers with different transistor types, such as bulk MOSFETs, arranged in face-to-back configurations, with peripheral circuitry providing access to memory arrays, and utilizing self-aligned techniques for transistor fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to maintain increasing density, then capacity increases, but mobility improvement and short channel control deteriorate
Solution Approach 1:
The patent transitions from planar 2D transistor channels to 3D vertically stacked channels (tri-gate and nanowire structures). By adding the vertical dimension, the channel length is extended without increasing the lateral footprint, enabling continued scaling while maintaining electrostatic control through the wrapped gate structure that surrounds the channel in three dimensions.
Solution Approach 2:
The patent employs composite material structures including silicon-germanium (SiGe) sacrificial layers combined with silicon active channels, and heterogeneous material stacks for memory arrays. These composite structures enable precise control of channel properties while maintaining fabrication compatibility, addressing both density and performance requirements.
2Ease of manufacture
If tri-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but mobility improvement and short channel control become difficult to maintain at small dimensions
Solution Approach 1:
The patent segments the transistor structure into distinct functional layers: sacrificial SiGe layers for defining channel geometry, silicon layers for active channels, and separated source/drain regions. This segmentation allows independent optimization of each layer's properties while maintaining overall device performance through controlled interfaces between segments.
Solution Approach 2:
The patent utilizes parameter changes in material composition (SiGe ratio), layer thicknesses, and doping concentrations to simultaneously achieve cost-effective bulk silicon processing and precise control of channel electrical properties. By adjusting these parameters, the device maintains high mobility and short channel control despite simplified fabrication.
Data Source
AI summary
Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are variously stacked in respective face-to-back arrangements. In an embodiment, three active layers each correspond to a different respective transistor type, wherein two active layers comprise transistors of respective memory arrays, and a third active layer comprises transistors of circuitry which is coupled to access the memory arrays. In another embodiment, hybrid bond structures are disposed between two of the active layers.