Heterogeneous Memory System with Unified Controller
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Solution Overview
Problem
Conventional computer systems face challenges in increasing memory capacity without adversely affecting the form factor, as DRAM-based main memory is volatile, power-consuming, and limited in density, requiring multiple DIMMs which increase cost and volume, making it unsuitable for mobile devices.
Innovation Solution
A memory system comprising plural heterogeneous memories with different latencies, where a high-capacity non-volatile memory operates as a cache for a high-speed memory, and both are controlled by dedicated controllers to optimize data storage and retrieval, allowing for efficient use of both volatile and non-volatile memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM-based main memory is used to increase storage capacity, then memory capacity is improved, but volume and cost increase due to requiring multiple DIMMs
Solution Approach 1:
The patent combines volatile memory (DRAM) and non-volatile memory (NAND flash) into a single memory system that functions as unified main memory. This merging allows the system to achieve high storage capacity using a single package rather than multiple DIMMs, thereby reducing system volume while maintaining or improving memory capacity.
Solution Approach 2:
The memory system is designed to perform multiple functions: it operates as volatile memory during active computing for high-speed access, and as non-volatile storage for persistent data retention. This multi-functionality allows a single memory device to replace both traditional main memory and secondary storage, reducing the overall system volume required.
2Quantity of substance
If DRAM-based main memory is used, then memory capacity is improved, but power consumption increases due to constant capacitor recharging
Solution Approach 1:
The patent merges DRAM and NAND flash memory into a unified system where each memory type is used for its optimal function. The non-volatile NAND flash portion does not require constant power for data retention, significantly reducing overall power consumption compared to using DRAM alone for the same capacity.
Solution Approach 2:
The system employs periodic data transfer between the volatile and non-volatile portions of the memory system. Frequently accessed data remains in the volatile DRAM portion for fast access, while less frequently accessed data is periodically moved to the non-volatile NAND flash portion, reducing the power required for constant DRAM refresh operations.
3Quantity of substance
If DRAM-based main memory is used, then memory capacity is improved, but device complexity increases due to requiring multiple DIMMs and controllers
Solution Approach 1:
The patent combines multiple memory types and their control functions into a single integrated memory device with a unified memory controller. This integration eliminates the need for multiple separate DIMMs and multiple independent controllers, thereby reducing memory system complexity while maintaining high storage capacity.
4Speed
If cache memory is added between processor and main memory, then access speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the cache memory function into the unified memory system by utilizing the volatile DRAM portion as a cache for the non-volatile NAND flash portion. This integration provides caching functionality without requiring a separate physical cache device, thereby improving access speed while minimizing the increase in device complexity.
Data Source
AI summary
A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.