Heterogeneous Metal Interconnect Lines for Sub-10 nm IC Scaling
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Solution Overview
Problem
The scaling of integrated circuits to sub-10 nanometer nodes faces challenges due to variability in conventional fabrication processes, limiting the ability to further extend these processes, necessitating new methodologies or technologies for advanced integrated circuit structure fabrication.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor processing, combined with advanced trench isolation and doping techniques, to enhance transistor density and performance by achieving tighter pitch and spacing in grating structures and maintaining desirable fin stress for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-10 nanometer nodes
Solution Approach 1:
The fabrication process is divided into multiple sequential stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage breaks down the complex task of creating sub-10nm features into manageable steps with intermediate structures, allowing precise control at each phase rather than attempting single-step patterning
Solution Approach 2:
Grating structures are formed preliminarily before the final fin structures are created. These preliminary grating patterns serve as templates that guide subsequent patterning steps, enabling achievement of sub-10nm precision through pre-planned, staged fabrication sequences
2Manufacturing precision
If pitch quartering and merged fin pitch quartering are implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Multiple pitch multiplication techniques (pitch doubling and pitch quartering) are merged into a single integrated fabrication flow. The merged fin pitch quartering combines grating structure formation with fin structure creation, reducing the need for separate processing sequences and managing complexity through consolidation
Solution Approach 2:
The fabrication approach transitions from two-dimensional planar patterning to three-dimensional grating structures with controlled pitch and spacing. By adding the vertical dimension and utilizing grating geometries, precise sub-10nm features are achieved through structural complexity rather than process complexity
3Productivity
If transistor density is increased, then productivity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The fabrication process utilizes controlled changes in critical parameters including grating pitch, grating spacing, and etch depths to achieve high transistor density. By systematically varying these parameters through the staged fabrication process, sub-10nm features are produced with precise dimensional control despite increased density requirements
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.