Heterogeneous Metal Interconnect Lines for Sub-10nm IC Scaling
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to the 10 nanometer node or smaller, due to variability in conventional methods, which limits the integration of new technologies and methodologies required for advanced integrated circuit structure fabrication.
Innovation Solution
The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor processing, combined with multi-layer trench isolation and fin trim isolation techniques, to enhance line density and transistor density while maintaining desirable fin stress for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple distinct stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage performs a specific function (forming mandrels, forming spacers, selective removal) to progressively achieve the final high-precision structure, breaking down the complex task of creating sub-10nm features into manageable sequential steps
Solution Approach 2:
Mandrel structures are formed in advance before the final fin structures are created. These preliminary mandrels serve as templates that guide subsequent spacer formation and material deposition, enabling precise positioning of final features without directly patterning them at the final dimensions
2Productivity
If feature size is scaled down to increase device density, then productivity is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The spacer structures self-align to the mandrels through conformal deposition processes, automatically establishing precise spacing and positioning without requiring additional alignment steps. The final fin structures self-organize around the spacer templates, with the spacer width directly determining the fin pitch, eliminating overlay errors and reducing variability
Solution Approach 2:
The critical dimension control transitions from being lithography-limited to being deposition-thickness-limited. By controlling the spacer film thickness through atomic layer deposition or chemical vapor deposition, the fin pitch can be precisely controlled at dimensions below the lithographic resolution limit, achieving sub-10nm precision
3Reliability
If heterogeneous metal line compositions are implemented, then device performance is improved, but device complexity increases
Solution Approach 1:
Different metal materials are selectively placed in different interconnect layers based on local performance requirements. Lower layers use copper for low resistance, while upper layers use cobalt or other materials optimized for specific electrical characteristics. Each metal region is tailored to the local current density and performance needs, achieving optimal overall device performance
Solution Approach 2:
The interconnect system employs composite material structures combining multiple metals (copper, cobalt, tungsten) with different electrical and mechanical properties. Barrier layers and liner layers are integrated with the metal fill materials to create composite structures that simultaneously provide electrical conductivity, diffusion blocking, and stress management
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.