Heterogeneous Metal Interconnect Lines for Sub-10nm Fabrication Variability

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The scaling of features in integrated circuits to the 10 nanometer node and smaller sizes is hindered by variability in conventional fabrication processes, limiting the possibility of further extension into advanced technology nodes.

Innovation Solution

The implementation of pitch quartering and merged fin pitch quartering approaches in semiconductor fin fabrication, combined with the use of three-layer trench isolation structures and fin trim isolation techniques, to enhance the precision and density of integrated circuit structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication processes are used for scaling, then existing manufacturing capabilities are maintained, but manufacturing precision deteriorates at 10 nanometer node and smaller sizes

Engineering Contradiction:

Improvefeature size precisionVSAvoidprocess variability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The fabrication process is divided into multiple sequential stages including pitch doubling, pitch quartering, and merged fin pitch quartering. Each stage breaks down the complex task of creating sub-10nm features into manageable steps with intermediate patterning operations, allowing precise control at each phase rather than attempting single-step patterning at the final dimension

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Mandrel structures and spacer layers are formed in advance before the final pattern transfer. The pitch quartering process uses preliminary mandrel formation followed by spacer deposition and removal cycles, preparing the structure progressively before reaching the final sub-10nm features, thereby reducing variability in the ultimate pattern

Inventive Principle:

Principle #10Preliminary action

2Productivity

If feature size is reduced to increase device density, then capacity increases, but manufacturing precision deteriorates due to process variability

Engineering Contradiction:

Improvedevice densityVSAvoidfeature size control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar patterning to three-dimensional fin structures through merged fin pitch quartering. By creating vertical fins with controlled widths and spacing, the process achieves higher effective density while maintaining precise lateral dimensions through self-aligned spacer formation rather than relying solely on lithographic resolution

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Spacer materials serve as intermediaries between lithographically defined mandrels and final metal interconnect patterns. The spacers provide a self-aligned pattern transfer mechanism that achieves sub-lithographic resolution, enabling precise feature size control at dimensions smaller than direct lithography can reliably produce

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If pitch quartering and merged fin pitch quartering are implemented, then manufacturing precision improves, but device complexity increases

Engineering Contradiction:

Improvepattern accuracyVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple pitch multiplication operations are merged into a single integrated process flow. The merged fin pitch quartering combines mandrel formation, spacer deposition, and pattern transfer steps that would otherwise be separate, reducing the total number of lithography cycles and simplifying process integration while maintaining sub-10nm precision

Inventive Principle:

Principle #5Merging (Combining)

4Manufacturing precision

If three-layer trench isolation and fin trim isolation techniques are used, then manufacturing precision improves, but ease of manufacture deteriorates

Engineering Contradiction:

Improveisolation structure precisionVSAvoidfabrication simplicity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Isolation structures are applied selectively to specific regions rather than uniformly across the entire wafer. The three-layer trench isolation and fin trim techniques are used locally where precise dimensional control is critical, such as around active fins and interconnect contacts, while other regions use simpler isolation, optimizing the balance between precision and manufacturing complexity

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250072078A1Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Publication Date: 2025.02.27 INTEL CORP

AI summary

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.