Heterogeneous Microprocessor for Energy-Scalable Sensor Inference
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Solution Overview
Problem
Embedded computing systems face a challenge in balancing computational flexibility with power efficiency, as hardware specialization for energy constraints limits flexibility and programmable accelerators struggle with energy efficiency due to high programmability overhead and complex mapping of computations.
Innovation Solution
A heterogeneous microprocessor is designed with a central processing unit, a programmable feature-extraction accelerator using Gene-Computation Cores and a support-vector machine accelerator, along with a Power Management Unit for fine-grained clock gating, enabling both feature extraction and classification while controlling energy consumption through genetic programming and error-aware modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If hardware specialization is used to address power constraints, then power efficiency is improved, but computational flexibility is limited
Solution Approach 1:
The processor is divided into heterogeneous cores with specialized functions: Gene-Computation cores for feature extraction, SVM cores for classification, and a CPU for control. Each core type is optimized for specific computational tasks, allowing the system to segment workloads according to energy efficiency requirements while maintaining overall flexibility through core selection.
Solution Approach 2:
The processor architecture provides multi-functionality by integrating multiple types of cores (Gene-Computation, SVM, CPU) that can be selectively activated based on workload requirements. The GPMM manager coordinates these diverse cores to handle various computational tasks, making the system universally applicable to different sensor inference problems while maintaining energy efficiency through selective activation of appropriate cores.
2Adaptability or versatility
If programmable accelerators are used to maintain flexibility, then computational flexibility is improved, but energy efficiency deteriorates due to high programmability overhead
Solution Approach 1:
The Gene-Computation cores utilize genetic programming to automatically generate and optimize their own execution pipelines and feature extraction algorithms. This self-service capability eliminates the need for external programming overhead, as the cores autonomously adapt to different sensor inference tasks through evolutionary optimization, thereby maintaining flexibility without the energy penalty of traditional programmable accelerators.
Solution Approach 2:
The architecture dynamically changes execution parameters by selecting different Gene-Computation cores with varying levels of genetic programming optimization based on the specific computational task. This allows the system to adjust the balance between programmability and energy efficiency in real-time, activating highly optimized cores for energy-critical tasks while using more flexible cores for tasks requiring adaptability.
3Adaptability or versatility
If complex mapping of computations is implemented in programmable accelerators, then computational flexibility is improved, but device complexity increases
Solution Approach 1:
The GPMM (Gene-Computation Manager) serves as an intermediary layer between the high-level computational tasks and the heterogeneous cores. It automatically maps sensor inference problems to appropriate Gene-Computation cores by generating genetic programs that describe the desired feature extraction and classification logic, eliminating the need for complex manual mapping while maintaining computational flexibility.
Solution Approach 2:
The architecture replaces complex mechanical mapping systems with biological evolution mechanisms. Instead of manually programming computation mappings, the system uses genetic programming to evolutionarily optimize the mapping between sensor data and feature extraction operations, substituting complex deterministic mapping algorithms with stochastic evolutionary processes that automatically adapt to different computational requirements.
Data Source
AI summary
A heterogeneous microprocessor configured to perform classification on an input signal. The heterogeneous microprocessor includes a die with a central processing unit (CPU) a programmable feature-extraction accelerator (FEA) and a classifier. The FEA is configured to perform feature extraction on the input signal to generate feature data. The classifier is configured to perform classification on the feature data and the CPU is configured to provide processing after classification. The FEA may be configured with a plurality of Gene-Computation (GC) Cores. The FEA may be configured for genetic programing with gene depth constraints, gene number constraints and base function constraints. The classifier may be a support-vector machine accelerator (SVMA). The SVMA may include training data based on error-affected feature data. The heterogeneous microprocessor may also include an automatic-programming & classifier training module. An automatic-programming & classifier training module may be configured to receive input-output feature data and training labels and generate gene code and a classifier model.