Heterogeneous Microprocessor with Shared Hardware Registers for x86 and ARM
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Solution Overview
Problem
Computing device manufacturers and users face challenges in supporting both x86 and ARM architecture processors due to the dilemma of which architecture to invest in, as software availability and performance differ between the two, leading to potential wasted investments when user needs change.
Innovation Solution
A microprocessor capable of running both x86 and ARM instruction set architectures by using a hardware instruction translator that translates instructions into microinstructions, allowing the execution pipeline to execute them directly, thereby enabling the microprocessor to operate in both modes without the need for software translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor is designed to support both x86 and ARM instruction set architectures, then the adaptability and versatility of the processor is improved, but the device complexity increases due to the need for multiple instruction translators and mode management mechanisms
Solution Approach 1:
The microprocessor is designed with a universal execution pipeline that can execute instructions from both x86 and ARM instruction set architectures. A single hardware platform provides multi-functionality by implementing both ISAs, allowing the same processor to run software for different architectures without requiring separate hardware designs for each ISA.
Solution Approach 2:
The patent employs instruction translators as intermediary components that convert x86 or ARM instructions into a common internal representation for the execution pipeline. This mediator approach allows the processor to support multiple ISAs by translating them into a unified execution model, managing the complexity through a layered architecture.
2Device complexity
If software translation is used to enable cross-architecture execution, then the device complexity is reduced, but the execution speed and performance deteriorate compared to native execution
Solution Approach 1:
The microprocessor dynamically switches between different execution modes (x86, ARM, or translated mode) based on the requirements of the executing software. The system can transition between native execution for performance-critical paths and translated execution for compatibility requirements, optimizing the balance between speed and versatility at runtime.
Solution Approach 2:
The instruction translators perform preliminary translation of instructions before they reach the execution pipeline, preparing the instructions in advance. This preliminary action allows the execution pipeline to operate efficiently with pre-translated instructions, reducing the overhead of translation during critical execution paths.
3Device complexity
If manufacturers invest in a single architecture (x86 or ARM), then the manufacturing cost and complexity are reduced, but the adaptability to changing user needs and software availability deteriorates
Solution Approach 1:
The microprocessor implements a universal architecture that supports multiple instruction set architectures (x86 and ARM) within a single hardware design. This universality allows manufacturers to create a single platform that can run software for different architectures, eliminating the need for separate hardware lines and providing adaptability to changing user needs and software availability.
Solution Approach 2:
The system changes operational parameters by switching between different instruction set modes (x86 mode, ARM mode, or translated mode). This parameter change approach allows the same hardware to adapt its behavior based on the requirements of the executing software, providing versatility without requiring physical hardware changes.
Data Source
AI summary
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.