Heterogeneous Microprocessor Preserving Non-ISA State During Architecture Switching
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Solution Overview
Problem
Computing device manufacturers and users face challenges in supporting multiple instruction set architectures, leading to wasted investments due to the need for separate hardware and software for x86 and ARM architectures, as demand shifts between these architectures, making it beneficial to develop devices that can run both x86 and ARM programs.
Innovation Solution
A microprocessor capable of operating as both an x86 and an ARM instruction set architecture, with dedicated storage for each architecture's state and a hardware instruction translator that converts instructions into microinstructions for execution, allowing seamless switching between architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware and software are developed for x86 and ARM architectures, then each architecture can be optimized for its specific performance requirements, but the device complexity increases and manufacturers face wasted investments when demand shifts between architectures
Solution Approach 1:
The microprocessor is designed to support multiple instruction set architectures (x86 and ARM) within a single device, allowing it to perform diverse computing functions. The processor includes separate execution pipelines for x86 and ARM instructions, enabling it to operate as either architecture without requiring separate hardware systems. This multi-functionality eliminates the need for manufacturers to produce separate devices for different architectures, reducing investment waste and simplifying the overall system.
2Adaptability or versatility
If a microprocessor supports multiple ISAs with separate execution pipelines, then it can execute both x86 and ARM programs efficiently, but the device complexity and initial cost increase
Solution Approach 1:
The microprocessor is divided into separate execution pipelines - an x86 execution pipeline and an ARM execution pipeline - that operate independently but share common resources such as the register file, memory interface, and control logic. This segmentation allows each ISA to be executed with dedicated optimization while avoiding the complexity of having completely separate processors. The shared resources reduce the overall device complexity compared to having fully independent x86 and ARM processors.
3Productivity
If hardware instruction translation is implemented for ISA switching, then performance improves compared to software translation, but the device complexity and cost increase
Solution Approach 1:
A hardware instruction translator is introduced as an intermediary component between the external ISA (x86 or ARM) and the internal execution pipeline. The translator converts instructions from the selected external ISA into internal microinstructions that can be executed by the shared execution units. This hardware translation mechanism provides fast, deterministic translation without the overhead of software interpretation, achieving high performance while the translator itself is implemented as a relatively simple hardware module rather than a complex system.
Data Source
AI summary
A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.