Heterogeneous Multi-Core Process Switching Across Asymmetric Architectures
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Solution Overview
Problem
Existing information processing devices with heterogeneous multi-cores face challenges in achieving both low-power consumption and high performance, as existing methods require compatible instruction set architectures (ISAs) for asymmetric cores, limiting performance and power efficiency differences.
Innovation Solution
An information processing device with a first and second processor core, where the ISAs and register sets do not need compatibility, using a memory to store execution codes and a switch process code that allows seamless switching between the cores by translating and optimizing the application process, enabling continuous execution across asymmetric cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If asymmetric cores with compatible ISAs are used for heterogeneous multi-processing, then power consumption is reduced and performance is improved, but the difference in performance and power efficiency between cores is limited to several times at most
Solution Approach 1:
The patent segments the execution code into basic blocks and creates separate execution code versions for each core type. The compilation process generates core-specific basic blocks that can be selectively executed on different core architectures, allowing each core to run optimized code for its specific architecture while maintaining seamless switching capability through the basic block interface.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a unified basic block interface and switching control logic. This intermediary layer translates between different ISA implementations by mapping operations to common basic blocks that can be executed on either core type, enabling seamless process switching without requiring full ISA compatibility between cores.
2Productivity
If a single CPU core operates at high frequency for high performance, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic core selection and switching between asymmetric cores based on real-time power and performance requirements. The system can dynamically switch between low-power mode (using only the low-power core) and high-performance mode (using the high-performance core or both cores), allowing adaptive adjustment of power consumption and processing speed according to actual workload demands.
Solution Approach 2:
The patent changes the operational parameters by introducing asymmetric cores with different frequency and voltage characteristics. The high-performance core operates at higher frequency and voltage for fast processing, while the low-power core operates at lower frequency and voltage for energy-efficient operation. The system dynamically adjusts which core operates at what parameters based on workload requirements.
3Use of energy by moving object
If DVFS is used to change operation frequency and voltage, then power consumption is reduced, but it is difficult to obtain characteristics satisfying both low-power consumption and high performance in a single core architecture
Solution Approach 1:
The patent employs asymmetric core architecture where two cores with fundamentally different performance and power characteristics coexist in the same system. Instead of trying to make a single core adaptive through DVFS, the system uses inherently asymmetric cores - one optimized for low power and another for high performance - allowing simultaneous optimization of both power consumption and performance without relying on frequency/voltage scaling of a single core.
Data Source
AI summary
An application process is switched between asymmetric processor cores having no compatibility in instruction set architectures so that the process can be continuously executed. In an information processing device, when a request to switch an execution subject is generated while a first processor core is executing an application program, a switch process code makes the first processor core specify a basic block being executed at present. The switch process code makes the first processor core execute a first execution code until a branch instruction at the end of the specified basic block, and makes a second processor core execute a second execution code from an instruction at the head of a basic block to be executed next to the specified basic block.