Multi-thread Processor with Heterogeneous Hardware Resources
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Solution Overview
Problem
Existing multi-threaded processor systems are inefficient as they require all hardware threads to have the same capabilities, leading to unnecessary resource usage and increased area and power requirements, as they are designed with a one-size-fits-all approach, which is not suitable for applications where threads have varying workloads and requirements.
Innovation Solution
A microprocessor architecture that allows individual hardware threads to have different capabilities, including varying instruction sets and register sets, with additional hardware to detect and handle unsupported instructions, enabling threads to be optimized for specific tasks by adding or removing resources as needed, and supporting different instruction sets and features on a thread-by-thread basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all hardware threads are designed with the same capabilities (homogeneous threads), then the processor architecture is simplified and easier to manufacture, but hardware area and power consumption increase due to unnecessary resources for threads with lighter workloads
Solution Approach 1:
The patent applies local quality by allowing different hardware threads to have different capabilities and resource allocations. Specifically, some threads are configured with full instruction sets and complete hardware resources, while other threads are configured with reduced instruction sets and fewer resources based on their specific workload requirements. This enables each thread to have locally optimized quality matching its functional needs, reducing overall hardware area while maintaining manufacturability through a standardized framework.
2Area of stationary object
If hardware resources are reduced for specific threads to optimize area, then hardware area and power consumption decrease, but the ability to execute all instruction sets on all threads is lost
Solution Approach 1:
The patent implements dynamics by making thread capabilities configurable and adaptable rather than static and uniform. The processor allows dynamic assignment of different instruction set architectures and resource configurations to different hardware threads based on runtime requirements. This enables the system to adaptively allocate full or reduced capabilities to specific threads, maintaining versatility where needed while optimizing area where possible.
Solution Approach 2:
The patent applies segmentation by dividing the processor into multiple independent hardware threads, each capable of having its own instruction set configuration and resource allocation. This segmentation allows the system to partition full functionality across only the threads that require it, while other threads can operate with reduced configurations, thereby reducing overall hardware area while maintaining the ability to support diverse instruction sets through the segmented thread architecture.
3Use of energy by stationary object
If threads are optimized for specific tasks with reduced hardware, then power consumption and area are reduced, but additional hardware is needed to detect and handle unsupported instructions
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of instruction decoding logic that mediates between the reduced-capability hardware threads and the full instruction set architecture. This intermediary decodes incoming instructions and determines whether they are supported by the current thread's configuration, raising exceptions for unsupported instructions. This mediation approach enables reduced hardware complexity while maintaining compatibility with the full instruction set through software exception handling.
4Device complexity
If homogeneous thread design is used, then resource allocation is simplified, but efficiency decreases when threads have varying workload requirements
Solution Approach 1:
The patent applies local quality by configuring different hardware threads with different resource allocations and capability levels matched to their specific workload requirements. Threads handling computationally intensive tasks receive full resources and instruction set support, while threads handling lighter tasks operate with reduced resources. This local optimization dramatically improves processing efficiency while the underlying framework maintains manageable resource allocation complexity.
Data Source
AI summary
A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to be available for executing an instructions has the hardware resources available required by that instructions and executing the instruction in dependence on the result of the determination.