Heterogeneous Multiprocessor Compilation via Base Platform Integration

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Solution Overview

Problem

Existing heterogeneous multiprocessor systems face challenges in integrating programmable ICs, such as FPGAs, to fully leverage their flexible hardware architecture within a heterogeneous computing environment, particularly in interacting with host systems and operating within the context of multiprocessor frameworks like OpenCL.

Innovation Solution

The integration of programmable ICs into a heterogeneous multiprocessor design allows for kernels to be compiled and transformed into hardware, enabling hardware acceleration by implementing them using programmable circuitry, which operates in cooperation with the host system, utilizing a base platform to facilitate communication between the programmable IC and the target platform.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If programmable ICs are integrated into heterogeneous multiprocessor systems, then hardware acceleration and flexibility are improved, but device complexity and integration difficulty increase

Engineering Contradiction:
Improvehardware flexibilityVSAvoidintegration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A base platform is introduced as an intermediary layer between the host system and the programmable IC. The base platform includes interface circuitry and control logic that facilitates communication and coordination, thereby simplifying the integration process while maintaining hardware flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The base platform is designed with universal interface capabilities that can work with different types of programmable ICs and host systems. This multi-functional design reduces integration complexity by providing a standardized interface layer that adapts to various configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If kernels are compiled and transformed into hardware implementations, then execution speed and performance are improved, but system complexity and compilation complexity increase

Engineering Contradiction:
Improvekernel execution speedVSAvoidcompilation system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The compilation and transformation of kernels into hardware implementations is performed in advance before execution. This preliminary action allows complex compilation processes to be completed beforehand, reducing runtime complexity while achieving high execution speeds through hardware acceleration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The compilation process is divided into distinct stages: kernel compilation, hardware transformation, and base platform integration. This segmentation allows each stage to be handled independently with specialized tools, reducing overall system complexity while enabling high-speed execution.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If programmable ICs are used for kernel implementation, then reconfigurability and adaptability are improved, but interaction with host system and integration difficulty worsen

Engineering Contradiction:
ImprovereconfigurabilityVSAvoidhost interaction ease
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The base platform serves as a mediator that simplifies host-system interaction with programmable ICs. It provides standardized interfaces and control mechanisms that make reconfigurable systems easier to operate, while the programmable IC maintains its full reconfigurability capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3218827B1Heterogeneous multiprocessor program compilation targeting programmable integrated circuits
Publication Date: 2020.05.27 XILINX INC
  • EP3218827B1 patent drawingFigure 1
  • EP3218827B1 patent drawingFigure 2~3
  • EP3218827B1 patent drawingFigure 4

AI summary

OpenCL program compilation may include generating (705), using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating (710) the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated (715) from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container (720).