Heterogeneous Non-Volatile Memory System for Write Speed and Data Retention
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Solution Overview
Problem
NAND flash memory devices in semiconductor memory systems face limitations in high-speed operation and data retention, requiring erase-before-write operations and leading to potential data loss during sudden power-offs due to their inability to perform overwrite operations efficiently.
Innovation Solution
A non-volatile memory system incorporating a combination of high-speed and low-speed non-volatile memory devices, where a controller coordinates concurrent write operations and ensures write completion signals are sent to the host when the faster device finishes, allowing the slower device to complete its write operation even after power-off, using techniques like polling checks or round robin signaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single NAND flash memory device is used, then the device can be manufactured with high degree of integration, but the system cannot operate at high speed and may lose data during sudden power-off
Solution Approach 1:
The memory system is segmented into two distinct non-volatile memory devices with different characteristics: a first device optimized for high-speed write operations and a second device optimized for data retention reliability. This segmentation allows each device to specialize in its strength, resolving the contradiction between speed and reliability.
Solution Approach 2:
The system changes the parameter of memory device type diversity by incorporating heterogeneous non-volatile memory devices with different write speeds and reliability characteristics. This parameter change enables the system to simultaneously achieve high-speed operation and data retention reliability that a single device type cannot provide.
2Reliability
If NAND flash memory performs erase-before-write operation, then the device can maintain data integrity, but the operation speed decreases due to additional erase steps
Solution Approach 1:
The write operation is segmented between two devices: the first non-volatile memory device performs fast write operations for speed-critical data, while the second device performs erase-before-write operations for reliability-critical data. This segmentation eliminates the need for slow erase operations to bottleneck the entire system.
Solution Approach 2:
The system applies partial erase-before-write action only to the second non-volatile memory device where reliability is paramount, while the first device performs full write operations without erase. This partial application of the erase protocol maintains data integrity where needed without sacrificing overall system speed.
3Reliability
If the system waits for the slower non-volatile memory device to complete write operation, then data integrity is ensured, but the perceived operation speed decreases
Solution Approach 1:
The controller performs preliminary write operations to the first non-volatile memory device which has faster write speed. This preliminary action allows the system to quickly acknowledge write completion to the host while the second device continues its slower write operation in the background, ensuring both speed and reliability.
Solution Approach 2:
The controller acts as an intermediary that manages the asymmetric write speeds of the two memory devices. It coordinates the write operations, determines when to signal completion to the host based on the first device's status, and ensures the second device completes its operation, thereby mediating between speed and reliability requirements.
Data Source
AI summary
A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.