Heterogeneous PG Cell Design for Power Efficiency and Area Reduction

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Solution Overview

Problem

Conventional design methods are unable to effectively handle both in-boundary and out-boundary power-ground (PG) cells within the same design block, leading to inefficiencies in power management and increased chip area in silicon chip designs, particularly in mobile devices and IoT applications.

Innovation Solution

A heterogeneous PG cell structure is implemented, utilizing both in-boundary and out-boundary PG cells in the same design block, with a design system that includes specialized tool kits and APIs to optimize power efficiency and minimize area, by aligning power strips with corresponding power rails and employing filler insertion to satisfy manufacturing constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional design methods are used to handle power-ground cells, then design simplicity is maintained, but power efficiency is reduced and chip area increases

Engineering Contradiction:

Improvepower efficiencyVSAvoidchip area

Core Design Contradiction:

Use of energy by moving objectVSArea of stationary object

Solution Approach 1:

The design block is segmented into multiple types of PG cells (in-boundary and out-boundary) with different power management characteristics. This segmentation allows each cell type to be optimized for specific functions, improving overall power efficiency while managing chip area through specialized layouts for each cell category.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the chip are assigned different PG cell structures based on local power requirements. In-boundary PG cells are used where power strips are contained within cell boundaries, while out-boundary PG cells are used where power strips extend beyond boundaries, allowing local optimization of power efficiency without uniformly increasing chip area.

Inventive Principle:

Principle #3Local quality

2Use of energy by moving object

If both in-boundary and out-boundary PG cells are integrated in the same block, then power efficiency is maximized, but design complexity increases

Engineering Contradiction:

Improvepower efficiencyVSAvoiddesign complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

A unified design system is created that can handle both in-boundary and out-boundary PG cells through a common framework. The system uses standardized APIs and tool kits that work with multiple PG cell types, allowing the design process to manage heterogeneous cells without proportionally increasing complexity, thus enabling power efficiency optimization across diverse cell structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12131109B2Block level design method for heterogeneous PG-structure cells

Publication Date: 2024.10.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.