Heterogeneous PLD Partitioning for Low-Power Timing Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices (PLDs) exhibit higher static power consumption compared to dedicated logic devices due to unused resources consuming power, even during active operation, which makes them unsuitable for low-power applications.
Innovation Solution
A heterogeneous architecture is implemented in PLDs, dividing resources into a power-optimized partition for low-power consumption and a performance-optimized partition for high performance, with non-critical timing paths mapped to the power-optimized partition and critical timing paths mapped to the performance-optimized partition, using low supply voltage for the former and high supply voltage for the latter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If PLD resources are disabled by de-coupling from operating voltage, then power consumption is reduced, but resources that are active during normal operation cannot have their power consumption reduced
Solution Approach 1:
The PLD architecture is segmented into multiple power domains, allowing different regions of the device to operate at different voltage levels. Configuration memory cells are divided into first and second sets, each associated with different programmable logic blocks, enabling independent power control of active resources without requiring complete device shutdown.
Solution Approach 2:
Different regions of the PLD are assigned different power characteristics - some regions operate at higher voltages for performance-critical functions while others operate at lower voltages for power-sensitive functions. This local differentiation allows active resources to have their power consumption adjusted based on specific functional requirements rather than uniform device-wide power control.
2Productivity
If PLD resources are kept enabled to maintain performance, then performance is maintained, but static power consumption increases due to unused resources
Solution Approach 1:
The PLD implements dynamic power management where configuration memory cells can be selectively enabled or disabled based on runtime conditions. Power domains can be dynamically adjusted to match actual resource utilization, allowing the device to transition between performance-optimized and power-optimized states without sacrificing the ability to meet timing requirements for active resources.
3Adaptability or versatility
If configuration memory cells are used to program PLD functionality, then programmability is achieved, but static power consumption increases due to memory cell leakage
Solution Approach 1:
The patent extracts the power-consuming configuration memory cells from the always-on logic fabric and places them in separately controllable power domains. This allows the memory cells to be powered down when not actively being used for configuration, separating the programmability function from continuous power consumption and enabling more aggressive power management of the configurable logic resources.
Data Source
AI summary
A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.