Heterogeneous Processing Bus for CPU, GPU, and FPGA Integration
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Solution Overview
Problem
Current techniques fail to effectively utilize diverse processor architectures, leading to underutilization of processors and slowed operation of mission-critical programs due to inefficient core allocation and resource management.
Innovation Solution
A hardware apparatus comprising a GPU, CPU, and FPGA, connected via a control and data bus assembly and API, allowing for heterogenous processing and efficient allocation of processing cores and memory, enabling the same code to run across different architectures and optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor architectures (CPU, GPU, FPGA) are integrated into a heterogeneous system, then resource utilization and processing capability are improved, but system complexity and integration difficulty increase
Solution Approach 1:
The patent introduces a heterogeneous processing manager as an intermediary component that coordinates between different processor architectures (CPU, GPU, FPGA). This manager handles task allocation, resource management, and communication protocols, thereby resolving the complexity of integrating multiple architectures while maintaining high resource utilization. The manager acts as a mediator that abstracts the heterogeneity from the application layer.
Solution Approach 2:
The system implements a universal interface layer that enables a single codebase to execute across multiple processor architectures. This universality is achieved through architecture-agnostic programming interfaces and automatic code translation mechanisms, allowing the same application to leverage CPU, GPU, and FPGA resources without requiring separate code versions for each architecture.
2Productivity
If processor cores are shared among multiple programs, then resource efficiency is improved, but operation speed of mission-critical programs deteriorates
Solution Approach 1:
The patent implements quality-of-service (QoS) policies that assign different priority levels to different programs based on their criticality. Mission-critical programs are allocated guaranteed time slots and reserved processing resources, ensuring their operation speed is not degraded by less critical tasks. Non-critical programs can utilize remaining resources, thereby achieving overall resource efficiency while protecting critical operations.
Solution Approach 2:
The processing system is segmented into different execution contexts and priority queues. The heterogeneous processing manager divides available processor cores into dedicated pools for different program categories, allowing simultaneous optimization for both speed (critical programs get dedicated fast paths) and efficiency (non-critical programs share remaining resources).
Data Source
AI summary
A system on a chip may include a GPU, a CPU, a dedicated memory for the CPU, an FPGA, a dedicated memory for the FPGA, a control and data bus assembly connecting the FPGA, the CPU, and the GPU, wherein the FPGA, the CPU, and the GPU are configured to interact using the control and data bus assembly and an API configured to allow the same code to run on the FPGA, the CPU, and the GPU, a VPX, a first HSIO connection connecting the GPU to the VPX, a second HSIO connection connecting the CPU to the VPX, and a third HSIO connection connecting the FPGA to the VPX.