Heterogeneous Processor Switching for Chip Area Reduction
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Solution Overview
Problem
Specialized processors designed for specific program domains lose performance when executing general-purpose programs due to energy inefficiency and increased chip area, necessitating their use under the control of general-purpose processors.
Innovation Solution
A computer architecture employing a set of heterogeneous processors that switch based on assessed data parallelism and control flow complexity, including a general-purpose processor and specialized processors tailored for specific execution needs, allowing for synergistic performance improvement without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specialized processors are used for specific program domains, then performance (speed and energy efficiency) is improved, but they lose performance when executing general-purpose programs due to energy inefficiency and increased chip area
Solution Approach 1:
The patent implements a heterogeneous processor system where multiple specialized processors (SIMD processor for data-parallel workloads, VLIW processor for control-flow heavy workloads, and general-purpose OOO processor) work together under a unified architecture. The switch unit dynamically routes instructions to the appropriate processor based on workload characteristics, enabling the system to handle both specialized and general-purpose programs efficiently without requiring separate dedicated systems.
Solution Approach 2:
The patent employs dynamic workload assessment and runtime profiling to determine which specialized processor should execute which program portions. The switch unit dynamically switches between processors based on real-time analysis of instruction characteristics, data parallelism levels, and control flow complexity. This dynamic adaptation allows the system to optimize performance for each specific workload while maintaining energy efficiency and avoiding unnecessary chip area usage.
2Speed
If multiple specialized processors are used to cover different program domains, then execution speed is improved, but energy consumption increases
Solution Approach 1:
The system dynamically selects which specialized processor to activate based on runtime profiling and workload assessment. The switch unit monitors program characteristics and routes instructions to the most appropriate processor, ensuring that energy-consuming specialized processors are only activated when their specific capabilities are needed. This dynamic switching minimizes energy consumption while maintaining high execution speed for diverse workloads.
Solution Approach 2:
The heterogeneous processor system includes automated workload assessment and runtime profiling mechanisms that self-determine the optimal processor allocation without requiring manual intervention. The switch unit autonomously analyzes instruction characteristics and data parallelism to route workloads to appropriate processors, enabling the system to self-optimize energy efficiency while maintaining performance across different program domains.
3Device complexity
If a general-purpose processor is simplified by using specialized processors, then chip area is reduced, but program allocation complexity increases
Solution Approach 1:
The system implements automated runtime profiling and workload assessment mechanisms that automatically determine the optimal processor allocation without requiring programmer intervention. The switch unit and profiling hardware work together to analyze program characteristics and dynamically route instructions to appropriate specialized processors, making the complex allocation process transparent to users and eliminating the need for manual program partitioning.
Solution Approach 2:
The switch unit acts as an intermediary between the instruction stream and the heterogeneous processors. It receives instructions, assesses their characteristics through runtime profiling, and automatically routes them to the most appropriate processor. This intermediary mechanism handles the complexity of program allocation internally, presenting a simplified interface to programmers while optimizing processor utilization based on workload characteristics.
Data Source
AI summary
A computer architecture employs multiple special-purpose processors having different affinities for program execution to execute substantial portions of general-purpose programs to provide improved performance with respect to a general-purpose processor executing the general-purpose program alone.