Heterogeneous Processor Virtual Core Mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current heterogeneous computing architectures for CPU cores face challenges in software support due to the difficulty in tracking and harnessing the heterogeneity of different CPU core types, leading to a lack of core heterogeneity support in mainstream operating systems.
Innovation Solution
The implementation of a heterogeneous processor architecture that hides heterogeneity from software by exposing virtual, homogeneous compute elements and dynamically maps them to appropriate physical cores based on performance and power characteristics, allowing for transparent optimization of task scheduling and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If heterogeneous computing architectures are implemented with multiple CPU core types, then computational efficiency and performance are improved, but software complexity and difficulty in tracking heterogeneous resources increase
Solution Approach 1:
The patent introduces a hardware-based virtualization layer that acts as an intermediary between software and physical heterogeneous cores. Virtual cores are created to present a homogeneous interface to software, while hardware automatically maps these virtual cores to appropriate physical cores based on task characteristics. This mediator layer shields software from heterogeneity complexity while enabling efficient utilization of diverse computational resources.
Solution Approach 2:
The patent creates virtual copies of cores that present a standardized interface to software. These virtual cores are copies that abstract away the underlying hardware diversity, allowing software to interact with uniform resources while the hardware layer handles the complexity of mapping to heterogeneous physical cores with different capabilities.
2Adaptability or versatility
If hardware dynamically maps virtual cores to physical cores, then adaptability to different workloads is improved, but hardware complexity increases
Solution Approach 1:
The patent implements dynamic mapping where the hardware automatically assigns virtual cores to physical cores based on real-time workload characteristics and system state. This dynamic behavior allows the system to adapt to different computational demands by selecting appropriate core types (e.g., high-performance vs. energy-efficient cores) without requiring software intervention or complex configuration.
Solution Approach 2:
The hardware layer autonomously performs the mapping decisions between virtual and physical cores without external control. The system self-manages the complexity of heterogeneous resource allocation through built-in hardware logic that monitors workload requirements and automatically selects optimal core assignments, freeing software from this management burden.
3Ease of operation
If heterogeneity is hidden from software through virtualization, then ease of operation is improved, but loss of information about actual resource characteristics occurs
Solution Approach 1:
The virtualization layer serves as an intermediary that preserves necessary information about physical core characteristics while presenting a simplified interface to software. The hardware maintains knowledge of which virtual cores map to which physical cores and their respective capabilities, enabling informed mapping decisions without exposing this complexity to software. Information about resource characteristics is retained in the hardware mapping layer rather than being lost.
Data Source
AI summary
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.