Heterogeneous Routing in Programmable Logic Devices
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Solution Overview
Problem
Programmable logic devices (PLDs) with heterogeneous routing architectures face challenges in optimizing power consumption, as existing methods do not effectively utilize the heterogeneity of interconnect resources to minimize overall power usage in user designs.
Innovation Solution
A two-step routing method is employed, where a performance-based first pass utilizes high-power interconnect resources, and a second pass identifies non-critical nets to reroute them to low-power resources, with power-saving benefits evaluated based on capacitance per load pin, ensuring minimal performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-power interconnect resources are used for all routing, then routing performance and speed are improved, but overall power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating interconnect resources into high-power and low-power types based on their performance characteristics. Critical nets that require high speed are routed through high-power interconnect resources, while non-critical nets are routed through low-power resources. This localized optimization allows each part of the interconnect structure to operate at the appropriate power level for its specific function, resolving the contradiction between overall performance and power consumption.
Solution Approach 2:
The patent changes the parameter of power consumption by introducing a two-pass routing approach. The first pass uses high-power resources for critical paths, while the second pass identifies non-critical nets and reroutes them to low-power resources. This parameter change is guided by a cost function that incorporates both performance requirements and power consumption characteristics, allowing the system to optimize the balance between speed and power usage dynamically.
2Use of energy by moving object
If low-power interconnect resources are used for all routing, then power consumption is reduced, but routing performance and speed deteriorate
Solution Approach 1:
The patent applies dynamics by making the routing resource selection adaptive rather than static. The two-pass routing process dynamically evaluates each net's criticality and assigns it to the appropriate interconnect resources. The cost function dynamically adjusts routing decisions based on performance requirements, allowing the system to flexibly allocate high-power resources only where necessary and use low-power resources elsewhere, thus resolving the contradiction between power reduction and performance maintenance.
3Use of energy by moving object
If heterogeneous routing architectures are implemented, then power optimization capabilities are improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the interconnect resources into distinct high-power and low-power segments. This segmentation is managed through a two-pass routing algorithm that treats different resource types separately. The first pass handles critical nets using high-power resources, while the second pass handles non-critical nets using low-power resources. This segmented approach simplifies the management of heterogeneity compared to a fully integrated resource pool, resolving the contradiction between power optimization capability and device complexity.
Data Source
AI summary
Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.