Heterogeneous III-V on Silicon Integration via Sacrificial Substrate
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Solution Overview
Problem
Current methods for wafer-scale integration of different semiconductor technologies are limited by lattice mismatch, thermal expansion mismatch, and lack of design flexibility, restricting the integration of multiple III-V devices with silicon technology, and existing three-dimensional integration techniques are inefficient for active devices and serial in nature.
Innovation Solution
A process for heterogeneous integration of III-V integrated circuits with silicon technology, enabling precise lateral registry and ultra-dense interconnection, using a dielectric bonding layer and alignment targets for accurate positioning of III-V devices on silicon substrates, allowing for the use of ultra-thin layers and mixed-semiconductor integration with thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heteroepitaxy is used for wafer-scale integration, then integration of different semiconductor technologies is achieved, but large defect density occurs due to lattice parameter mismatch
Solution Approach 1:
The patent segments the integration process into distinct stages: growing III-V devices on a sacrificial SiGe substrate, fabricating silicon devices on a separate silicon substrate, and then bonding the two substrates together. This segmentation allows each substrate to be optimized for its specific device type without lattice mismatch issues, as the SiGe substrate is later removed to eliminate defect propagation.
Solution Approach 2:
The patent introduces a sacrificial SiGe substrate as an intermediary layer that facilitates the growth of III-V devices. This intermediary substrate has a lattice constant that matches III-V materials, enabling defect-free growth. After device fabrication, the SiGe substrate is removed via selective etching, leaving the III-V devices suspended over the silicon substrate, thus preventing defect propagation to the final integrated structure.
2Adaptability or versatility
If wafer bonding is used to join silicon and III-V wafers, then device integration is achieved, but thermal expansion mismatch requires complete removal of III-V substrate
Solution Approach 1:
The patent extracts and removes the problematic SiGe substrate after it has served its purpose as a growth platform. By selectively etching away the SiGe layer through holes in the metal capping layer, the III-V devices are released and bonded to the silicon substrate without requiring removal of the entire III-V substrate, thus simplifying the manufacturing process.
Solution Approach 2:
The SiGe substrate serves as a disposable, sacrificial layer that is used temporarily during the fabrication process and then removed. This temporary substrate enables complex integration that would otherwise be difficult or impossible, and its removal is a planned and necessary step in the process, analogous to using a disposable tool or component that serves a specific function and is then discarded.
3Adaptability or versatility
If flip-chip technique is used for three-dimensional integration, then various device technologies can be integrated, but large package size results due to two-dimensional planar geometry
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking III-V devices over silicon devices using suspended growth substrates. This vertical stacking approach allows multiple device layers to be integrated in the thickness direction rather than spreading them out in the planar direction, significantly reducing the overall package footprint while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process achieves high alignment accuracy, ultra-dense interconnection, and thermal management, enabling the fabrication of highly integrated systems-on-a-chip with improved yield, reduced cost, and robustness, overcoming limitations of existing techniques by allowing multiple III-V devices and silicon integration with superior electrical, thermal, and mechanical performance.
Implementation Method 1
bonding the active device material block to the host circuit substrate by a dielectric bonding layer disposed on the host circuit substrate
Implementation Method 2
plurality of alignment targets forming a perimeter; utilizing the plurality of alignment targets to position the one or more active device structures
Implementation Method 3
at least one first thermal vias; at least one second thermal vias; fabricating at least one second interconnection between the plurality of first thermal vias and the plurality of second thermal vias
Data Source
AI summary
The present invention relates to a process for fabricating integrated circuit system. More particularly, the process allows for fabrication of highly integrated system-on-a-chip modules through heterogeneous integration of different semiconductor technologies wherein alignment targets on the base semiconductor are used for precise lateral positioning of device structures above.