Heterogeneous SoC Cores for Common-Mode Fault Mitigation
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Solution Overview
Problem
Integrated modular avionics systems face challenges in ensuring high data integrity due to undetected design flaws in processing hardware, which can lead to common mode faults and hazardous misleading information or loss of function, and existing redundancy methods like dual lockstep computing and TMR increase SWAP-C factors.
Innovation Solution
A heterogeneous system-on-a-chip (SoC) is fabricated with dissimilar processing cores, each following a common functional profile but distinct implementation profiles, including different fabrication standards and logical devices, to mitigate common mode faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual lockstep computing or triple modular redundancy is used to mitigate common mode faults, then reliability is improved, but device complexity and SWAP-C factors increase
Solution Approach 1:
The patent applies asymmetry by using dissimilar processing cores with different microarchitectures, instruction set architectures, and fabrication processes. Instead of symmetric redundancy (identical cores), the system uses heterogeneous cores that are fundamentally different in design, thereby breaking common mode faults while avoiding the full SWAP-C penalty of traditional redundant systems.
Solution Approach 2:
The patent changes multiple parameters simultaneously: fabrication process parameters (different foundries), architectural parameters (different ISA and microarchitecture), and implementation parameters (different logic families). This multi-parameter differentiation approach achieves reliability improvement without linearly increasing system complexity, as the cores share a common functional profile while differing in implementation details.
2Reliability
If multiple processing targets with different implementation profiles are used, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent achieves universality through a common functional profile that defines standardized interfaces, memory models, and communication protocols. This allows dissimilar cores with different implementation profiles to be manufactured using established semiconductor fabrication processes while maintaining system-level compatibility and reducing manufacturing complexity.
3Reliability
If heterogeneous processing cores with different implementation profiles are used, then undetected errors are reduced, but design complexity increases
Solution Approach 1:
The patent adds another dimension of differentiation by varying implementation profiles across multiple axes: fabrication process, logic family, microarchitecture, and instruction set architecture. This multi-dimensional differentiation approach reduces undetected errors more effectively than single-dimension redundancy while managing design complexity through a standardized functional profile framework.
Data Source
AI summary
A method for fabrication of a heterogenous system on a chip (SoC) or other like integrated circuit (IC) device provides at least two dissimilar processing cores sharing a common functional profile but differentiated as to how the common functional profile is implemented. For example, the common functional profile may define the physical and logical configuration of each core, the functions and/or languages executable thereon, and any external interconnects to other devices or systems. However, each core may have a distinct implementation profile differentiated from that of the other on one or more levels of decomposition, based on differences in the underlying configuration of logical devices, the circuit components of said logical devices, and/or the physical design parameters including process geometries, fabrication standards, and/or fabrication processes via which the functional profile is physically realized in each core.