Heterogeneous Processor Storage Device Memory Sharing
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Solution Overview
Problem
In electronic devices with accelerators, data exchange between controllers and accelerators often occurs through external host memory, leading to bottlenecks and performance issues due to increased load and memory limitations.
Innovation Solution
A storage device with heterogeneous processors, where a first processor and a second processor of a different type share a buffer memory, allowing direct communication and access to each other's memory spaces without external intervention, using virtual addresses to manage memory allocation and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data exchange between controller and accelerator is performed through external host memory, then data transfer is enabled, but bottlenecks occur and performance is reduced
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the controller and accelerator. This buffer memory serves as a local storage space that enables direct data exchange between the two processors without requiring external host memory involvement, thereby eliminating the performance bottleneck while maintaining data transfer capability
Solution Approach 2:
The patent extracts the data exchange function from the external host memory system and relocates it to a local buffer memory within the storage device. This separation allows the controller and accelerator to communicate independently of the host memory, removing the performance constraint imposed by external memory access
2Speed
If direct communication between controller and accelerator is implemented, then processing speed is improved, but memory capacity is reduced and load increases
Solution Approach 1:
The patent merges the buffer memory functionality into the storage device's existing memory architecture, allowing the same memory resources to serve multiple purposes. The buffer memory is integrated into the storage controller's memory space, enabling direct communication between controller and accelerator while utilizing already-allocated memory resources rather than adding separate memory capacity
Solution Approach 2:
The buffer memory serves multiple functions: it acts as working memory for the controller, provides temporary storage for the accelerator, and enables direct data exchange between the two processors. This multi-functionality allows fast direct communication without requiring dedicated memory capacity solely for this purpose
3Productivity
If heterogeneous processors share memory space, then performance is improved by reducing data copying, but memory management complexity increases
Solution Approach 1:
The patent implements self-service memory management where the controller automatically manages the buffer memory allocation and address mapping for the accelerator. The controller's processor handles the complexity of virtual address translation and memory space management, allowing the accelerator to access memory without requiring its own separate memory management hardware or software
Data Source
AI summary
A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.