Heterogeneous Thread Scheduling for Opportunistic Accelerator Offload

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Solution Overview

Problem

The challenge of deploying accelerator solutions in heterogeneous computing environments is exacerbated by the complexity of managing diverse accelerator mixes across different platforms and operating systems, leading to inefficiencies in energy consumption and performance due to the need for specialized hardware devices that are not universally compatible.

Innovation Solution

A heterogeneous scheduler dynamically migrates threads between processing elements based on workload characteristics, uses a multiprotocol link for device communication, and employs ABEGIN/AEND instructions for opportunistic accelerator use, along with code translation and work queue management to optimize power consumption and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If specialized hardware accelerators are used for specific computing tasks, then performance and energy efficiency are improved, but device compatibility and system complexity worsen

Engineering Contradiction:
Improvecomputing performanceVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a heterogeneous scheduler that can dynamically allocate threads to different types of processing elements (CPUs, GPUs, FPGAs, ASICs) based on workload characteristics. This universal scheduling approach allows a single software layer to manage multiple accelerator types, providing the benefits of specialized hardware without requiring separate management systems for each device type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The heterogeneous scheduler acts as an intermediary layer between the operating system and diverse accelerators. It translates high-level thread allocation requests into device-specific execution commands, managing the complexity of heterogeneous hardware through a unified software interface that abstracts away device-specific details.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If diverse accelerator mixes are deployed across different platforms, then computing performance is improved, but ease of operation and programming model compatibility worsen

Engineering Contradiction:
Improvecomputing performanceVSAvoidprogramming model compatibility
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The heterogeneous scheduler serves as a mediator that presents a homogeneous programming model to applications while managing diverse accelerators underneath. Applications can submit threads using a unified interface, and the scheduler handles the complexity of mapping these threads to appropriate accelerator types, maintaining programming simplicity despite hardware diversity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The scheduler implements a universal programming model that works across all accelerator types. By providing a single, consistent interface for thread submission and management, it enables programmers to exploit the performance benefits of various accelerators without learning multiple programming paradigms or device-specific interfaces.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Stability of the object's composition

If threads are statically assigned to specific processing elements, then system stability is improved, but adaptability to workload changes and energy optimization worsen

Engineering Contradiction:
Improvesystem stabilityVSAvoidworkload adaptability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The heterogeneous scheduler implements dynamic thread migration capabilities that allow threads to be moved between different processing elements based on changing workload characteristics and system conditions. This dynamic approach maintains system stability through controlled management while adapting to varying computational demands and optimizing energy consumption by selecting appropriate execution devices.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The scheduler incorporates feedback mechanisms that monitor workload characteristics, processor utilization, and energy consumption. Based on this feedback, it dynamically adjusts thread allocation decisions, migrating threads between CPUs and accelerators to optimize performance and energy efficiency while maintaining system stability through controlled adaptation.

Inventive Principle:
Principle #23Feedback

4Use of energy by moving object

If opportunistic accelerator utilization is implemented, then energy efficiency is improved, but device complexity and scheduling overhead worsen

Engineering Contradiction:
Improveenergy efficiencyVSAvoidscheduling complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The heterogeneous scheduler implements self-service mechanisms where the scheduling system automatically monitors system state, identifies suitable accelerator opportunities, and executes thread migration decisions without external intervention. This automation manages the complexity of opportunistic scheduling while achieving energy efficiency benefits.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The scheduler uses feedback from system monitoring to identify opportunistic accelerator utilization scenarios. By continuously monitoring workload characteristics and accelerator availability, it automatically makes informed decisions about thread migration to improve energy efficiency while managing scheduling complexity through systematic feedback-driven control.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4398113B1Systems, methods, and apparatuses for heterogeneous computing
Publication Date: 2025.12.10 INTEL CORP
  • EP4398113B1 patent drawingFigure 1
  • EP4398113B1 patent drawingFigure 2
  • EP4398113B1 patent drawingFigure 3

AI summary

The present disclosure provides a processor including a processor core. The processor core includes: a decoder to decode at least one instruction native to the processor core; one or more execution units to execute at least one decoded instruction, the at least one decoded instruction corresponding to an acceleration begin instruction, the acceleration begin instruction to indicate a start of a region of code to be offloaded to an accelerator.