Heterogeneous Transceiver Channels for Wide-Range PLD Data Rates
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Solution Overview
Problem
Designing programmable logic devices (PLDs) that can support a wide range of high-speed serial data communication speeds, particularly at upper ranges such as 6 Gbps and up to 10-12 Gbps, is a significant challenge due to the need for flexible and efficient circuitry that can accommodate various communication protocols and data formats.
Innovation Solution
The implementation of serial data receiver circuitry with multiple channels adapted for different maximum serial bit rates, including at least one channel for lower speeds (up to 6 Gbps) and one for higher speeds (up to 10 Gbps), along with phase-locked loop (PLL) circuits that provide clock signals for each, allowing for flexible operation and compatibility between channels. Each channel includes associated decoder and transmitter circuitry, enabling transceiver functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLD is designed to support a wide range of high-speed serial data communication speeds (up to 10-12 Gbps), then the adaptability and versatility of the device is improved, but the device complexity increases due to the need for multiple types of circuitry to accommodate various communication protocols and data formats
Solution Approach 1:
The PLD is divided into multiple independent transceiver channels, each capable of operating at different data rates. The device includes both low-speed transceiver channels (supporting up to 6 Gbps) and high-speed transceiver channels (supporting up to 10-12 Gbps), allowing the system to be segmented into functional units with specialized capabilities for different communication speed requirements
Solution Approach 2:
The PLD implements a universal transceiver architecture where channels can be configured for different operating speeds and protocols. The device can function as both low-speed and high-speed transceivers, with the ability to support multiple communication protocols and data formats through programmable logic and configurable interface circuitry
2Adaptability or versatility
If multiple channels with different maximum serial bit rates are implemented, then the adaptability to various protocols is improved, but the manufacturing precision requirements increase to ensure proper operation across different speed ranges
Solution Approach 1:
Different channels are designed with locally optimized characteristics appropriate for their intended operating speeds. High-speed channels incorporate specialized circuitry optimized for 10-12 Gbps operation, while low-speed channels are optimized for up to 6 Gbps, allowing each channel to achieve manufacturing precision requirements tailored to its specific speed range rather than requiring all channels to meet the most stringent high-speed requirements
3Reliability
If dedicated PLL circuits are provided for each channel type, then the reliability of clock signal supply is improved, but the device complexity and area usage increase
Solution Approach 1:
The clock signal generation system is segmented into dedicated PLL circuits for different channel types. Low-speed channels have dedicated PLLs optimized for their frequency ranges, and high-speed channels have dedicated PLLs optimized for higher frequencies, ensuring reliable clock supply for each channel type without requiring a single complex PLL to handle all speed ranges
Data Source
AI summary
High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.