Heterojunction Photodiode Layout for Higher CMOS Image Sensor Sensitivity

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Solution Overview

Problem

Conventional CMOS image sensors face issues with reduced light sensitivity and increased crosstalk noise due to light being blocked or scattered by interconnection layers, and miniaturization of pixel units is restricted by photodiodes formed in the substrate.

Innovation Solution

A photosensitive device with photodiodes formed on the surface of the interconnection layer over the substrate, using a first and second material layer to create a p-n junction, allowing for enhanced light sensitivity and reduced noise by avoiding absorption and scattering issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If photodiodes are formed in the substrate for FSI or BSI CMOS image sensors, then the device can be manufactured with standard CMOS processes, but the photosensitive area is restricted and light sensitivity is reduced due to interconnection layer absorption and scattering

Engineering Contradiction:
ImprovemanufacturabilityVSAvoidlight sensitivity
Core Design Contradiction:
Ease of manufactureVSIllumination intensity

Solution Approach 1:

The photodiode is moved from a planar configuration within the substrate to a three-dimensional stacked configuration, with the photosensitive region extending vertically above the substrate surface. This vertical extension allows the photodiode to capture light from multiple angles and increases the effective photosensitive area without occupying additional lateral pixel space, thereby improving light sensitivity while maintaining standard CMOS manufacturing processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The photodiode structure is segmented into distinct functional regions: a photosensitive region extending vertically above the substrate, a drift region for charge collection, and a substrate region. This segmentation allows each region to be optimized for its specific function, with the photosensitive region positioned to maximize light capture while the drift region efficiently collects generated charges, overcoming the limitations of traditional planar photodiodes.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If photodiodes are formed in the substrate, then the device structure is simplified, but miniaturization of pixel units is restricted for maintaining sufficient photosensitive areas

Engineering Contradiction:
Improvestructure complexityVSAvoidpixel unit size
Core Design Contradiction:
Device complexityVSArea of moving object

Solution Approach 1:

The invention transitions from a two-dimensional planar photodiode to a three-dimensional stacked photodiode structure. By extending the photosensitive region vertically above the substrate, the effective photosensitive area is increased without increasing the lateral footprint of the pixel unit. This enables pixel miniaturization while maintaining sufficient photosensitive area for adequate light capture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The photodiode structure is nested vertically, with the photosensitive region positioned above the substrate surface and the drift region extending downward into the substrate. This nested configuration allows the photodiode to utilize both the space above and within the substrate, maximizing the use of available volume within the pixel unit and enabling further miniaturization.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If lights pass through the interconnection layer to reach photodiodes in FSI sensors, then the sensor can be manufactured with standard processes, but light sensitivity is reduced due to absorption and scattering by the interconnection layer

Engineering Contradiction:
Improvemanufacturing process compatibilityVSAvoidlight absorption and scattering
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The harmful interconnection layer is extracted from the light path by positioning the photosensitive region vertically above the substrate surface, where incident light can directly illuminate the photodiode without passing through the interconnection layer. This extraction eliminates the absorption and scattering effects caused by the interconnection layer, significantly improving light sensitivity while maintaining compatibility with standard CMOS manufacturing processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of having light pass through the interconnection layer to reach the photodiode (conventional FSI approach), the invention inverts the configuration by positioning the photosensitive region above the substrate surface, allowing light to directly illuminate the photodiode from the front. This inversion eliminates the harmful effects of the interconnection layer while maintaining standard CMOS manufacturing compatibility.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves light sensitivity and response speed by allowing larger photosensitive areas and reducing crosstalk noise, as incident light is directly received by the photodiodes without being absorbed or scattered by the interconnection layer or substrate.

Implementation Method 1

the first material layer and the second material layer form a photodiode

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS12080734B2Photosensitive semiconductor device including heterojunction photodiode
Publication Date: 2024.09.03 UNITED MICROELECTRONICS CORP
  • US12080734B2 patent drawing
  • US12080734B2 patent drawing
  • US12080734B2 patent drawing

AI summary

A method for forming a photosensitive device includes the steps of providing an integrated circuit structure having a first pad and a second pad exposed from a surface of the integrated circuit structure, forming a first material layer on the surface of the integrated circuit structure, patterning the first material layer to expose the second pad, forming a second material layer on the first material layer and covering the second pad, and patterning the second material.