Heterojunction Semiconductor Device Reducing Parasitic Capacitance
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Solution Overview
Problem
Field effect transistors suffer from parasitic capacitances that deteriorate their operational properties, and undesirable package structures can increase these capacitances, affecting the device's performance.
Innovation Solution
The semiconductor device incorporates an active layer with source and drain electrodes, a gate electrode, a gate field plate, interlayer dielectric, and inter-source, inter-drain, and inter-gate layers, which include via holes and plugs for electrical connections, along with insulating layers and pads to reduce parasitic capacitances and enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional field effect transistor structure is used, then device functionality is achieved, but parasitic capacitances are generated that deteriorate operational properties
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode, second gate electrode, third gate electrode) positioned at different heights and locations. This segmentation allows independent control of electric fields in different regions, enabling reduction of parasitic capacitances between gate and source/drain while maintaining effective channel control.
Solution Approach 2:
The invention introduces vertical dimensionality by positioning gate electrodes at different heights (first gate at lowest level, second gate at intermediate level, third gate at highest level). This three-dimensional arrangement enables spatial separation of electric field control functions, reducing overlapping capacitances while maintaining effective gate control over the channel.
2Ease of operation
If gate electrode is positioned close to source and drain electrodes for effective control, then switching performance improves, but parasitic capacitance between gate and source/drain increases
Solution Approach 1:
The gate control function is segmented into multiple electrodes at different positions. The first gate electrode controls the channel region, while the second and third gate electrodes control the extension regions. This segmentation allows effective channel control without requiring the entire gate structure to be in close proximity to source and drain, thereby reducing parasitic capacitance.
Solution Approach 2:
Different gate electrodes are positioned with different spatial relationships to source and drain electrodes. The first gate electrode is positioned to optimize channel control, while the second and third gate electrodes are positioned to control extension regions with reduced overlap to source/drain. This local optimization of gate positioning reduces parasitic capacitance while maintaining effective control.
3Area of stationary object
If source pad overlaps with drain region to reduce device area, then area efficiency improves, but parasitic capacitance between source pad and drain increases
Solution Approach 1:
The source pad is positioned to partially overlap with the drain region rather than completely avoiding it or fully overlapping. This partial overlap (where the overlapping area is smaller than or equal to 40% of the drain region area) provides a compromise that achieves reasonable area efficiency while limiting parasitic capacitance generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitances, improves resistance values, and increases the breakdown voltage by dispersing the electrical field, thereby enhancing the performance and efficiency of the semiconductor device.
Implementation Method 1
an interlayer dielectric covers the source electrode, the drain electrode, the gate field plate, and the gate electrode
Implementation Method 2
increases the breakdown voltage by dispersing the electrical field
Data Source
AI summary
A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.