Normally Off Heterojunction Transistor via Sacrificial Layer Dopant Implant
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Solution Overview
Problem
Existing methods for manufacturing normally off-type high electron mobility transistors, such as those using gallium nitride, face challenges with imperfect control of dopant implantation leading to increased conduction resistance and threshold voltage variability due to defects and misplacement of dopants in the channel.
Innovation Solution
A method involving the formation of a precursor transistor with a substrate, buffer layer, and initial III-V semiconductor layer, followed by P-type dopant implantation and subsequent epitaxial growth of additional layers to create a controlled electric field and insulating zone, ensuring precise threshold voltage control and reduced conduction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type dopant implantation is performed to create an insulating zone at the heterojunction interface, then the transistor achieves normally off behavior with positive threshold voltage, but the implantation process introduces defects in the channel structure and causes imperfect dopant placement control
Solution Approach 1:
A sacrificial layer is introduced as an intermediary medium to receive the dopant implantation. This layer acts as a buffer that captures the implanted dopants without damaging the underlying channel structure. The sacrificial layer is subsequently removed, leaving behind a clean interface with the desired insulating zone formed by the dopants in the first semiconductor layer, thus mediating between the implantation process and the final device structure.
Solution Approach 2:
The structure is segmented into distinct functional layers: a first semiconductor layer where dopants are implanted to form the insulating zone, a sacrificial layer that temporarily holds the dopants during implantation, and a second semiconductor layer that forms the channel. This segmentation allows the dopant implantation to be performed in a controlled manner in the first layer without directly exposing the channel-forming second layer to the implantation damage.
2Measurement precision
If higher dopant implantation doses are used to ensure sufficient insulating zone formation, then the threshold voltage control improves, but the conduction resistance in the channel increases due to dopant placement in the channel region
Solution Approach 1:
The sacrificial layer serves as an intermediary that absorbs excess dopant implantation doses. By adjusting the thickness of the sacrificial layer, the implantation process can be optimized to place dopants primarily in the first semiconductor layer without over-doping the channel region. The sacrificial layer is then removed, leaving a precisely controlled dopant distribution that achieves the desired threshold voltage without excessive channel resistance.
Solution Approach 2:
The thickness of the sacrificial layer is used as a controllable parameter to optimize the dopant distribution. By carefully selecting the sacrificial layer thickness, the implantation process can be tuned to achieve the desired dopant concentration in the first semiconductor layer while preventing dopant migration into the channel-forming second layer, thus balancing threshold voltage control with low conduction resistance.
3Reliability
If multiple epitaxial growth steps are performed to form the semiconductor layers, then the heterojunction quality and electron mobility improve, but the manufacturing complexity and production time increase
Solution Approach 1:
The sacrificial layer is deposited and prepared in advance before the dopant implantation step. This preliminary preparation allows the subsequent implantation and removal steps to be performed more efficiently, as the sacrificial layer is already in place to receive the dopants. The preliminary action of depositing the sacrificial layer simplifies the overall process by providing a ready-made buffer that eliminates the need for complex in-situ protection techniques during implantation.
Solution Approach 2:
The formation of the insulating zone through dopant implantation is merged with the epitaxial growth process. The dopant implantation into the first semiconductor layer is performed as part of the epitaxial sequence, and the subsequent removal of the sacrificial layer is integrated into the same fabrication run. This merging of steps reduces the total number of separate process cycles and improves manufacturing efficiency while maintaining heterojunction quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a normally off-type heterojunction transistor with improved electron mobility and reduced resistive losses, providing precise control over the threshold voltage and minimizing defects, thus enhancing the transistor's performance and reliability.
Implementation Method 1
a P-type dopant implant is formed in the first layer of type III-V semiconductor alloy
Implementation Method 2
a second layer of type III-V semiconductor alloy is formed by vapor phase epitaxy on the implant and the first layer of type III-V semiconductor alloy
Implementation Method 3
the electric field generated by the implant makes it possible to create an insulating zone at its vertical, at the interface between the binary layer of nitride and the ternary layer of nitride
Data Source
Figure 1~6
Figure 7~12
AI summary
The invention relates to a method for manufacturing a heterojunction transistor (1), comprising the steps of: - implantation of dopants to form an implant (81) in a first layer of III-V type semiconductor alloy (41); - removal of an upper part of the first layer (41) and of the implant (81) by maintaining epitaxial conditions; - interruption of the removal when the density at the upper face of the implant (81) is maximum; - formation of a second layer of III-V type semiconductor alloy (42) by vapor phase epitaxy on said implant (81) and the first layer; - formation of a third layer of III-V type semiconductor alloy (6) by vapor phase epitaxy so as to form an electron gas layer (5) at the interface between this third layer (6) and the second layer; - formation of a gate (73) above the third layer (6).