Semiconductor Heterostructure Memory Cell for Fast Write and Long Retention
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Solution Overview
Problem
Current semiconductor memory cells, such as DRAM and flash memory cells, face challenges in achieving a balance between fast write times and long storage durations, with DRAM having short storage times and flash memory experiencing durability issues due to slow write times and limited cycle durability.
Innovation Solution
A memory cell design incorporating a semiconductor heterostructure with a space charge zone, where the heterostructure moves within the space charge zone under retention voltage, allowing for quick writing and extended storage by trapping charge carriers within the heterostructure, ensuring secure storage of bit information with nanosecond access times and several years of storage duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If flash memory cells use SiO2 barriers to enclose a floating gate for long storage time, then storage time is improved (>10 years), but write time becomes slow (microseconds) and durability decreases (one million cycles)
Solution Approach 1:
The patent changes the material composition of the barrier layer from conventional SiO2 to a composite structure including AlO.5Ga0.5As and InP layers. This material parameter change enables both long storage time and fast write speed by creating appropriate potential barriers and tunneling conditions. The InP layer specifically enables hot carrier injection for fast writing while the AlO.5Ga0.5As provides the necessary barrier height for data retention.
Solution Approach 2:
The patent employs a composite barrier structure combining AlO.5Ga0.5As and InP layers. This composite material approach allows the system to simultaneously achieve the barrier properties needed for long-term storage and the tunneling properties required for fast write operations, resolving the contradiction between storage duration and write speed.
2Duration of action of stationary object
If flash memory cells use SiO2 barriers for long storage time, then storage time is improved (>10 years), but durability decreases (one million erase and write cycles)
Solution Approach 1:
The patent changes the barrier material from SiO2 to AlO.5Ga0.5As/InP composite structure. This parameter change reduces the harshness of the write process by enabling controlled quantum tunneling and hot carrier injection, thereby preserving the barrier integrity over millions of cycles while maintaining long storage time.
Solution Approach 2:
The patent converts the potentially harmful high-energy hot carriers into a beneficial writing mechanism. By designing the AlO.5Ga0.5As/InP barrier structure, hot carriers can be injected controllably to write data without causing excessive damage to the barrier, thus improving durability while enabling fast writing.
3Productivity
If DRAM memory cells store information as charge in a capacitor, then access time is fast (less than 20 nanoseconds), but storage time becomes short
Solution Approach 1:
The patent introduces a carefully engineered AlO.5Ga0.5As/InP barrier layer as an intermediary between the charge storage region and the external environment. This intermediary structure enables fast charge injection (like DRAM) while simultaneously providing the barrier needed for long-term charge retention (like flash memory), thus combining the advantages of both memory types.
Solution Approach 2:
The patent changes the barrier material parameters to achieve both fast writing and long storage. The specific composition and thickness of the AlO.5Ga0.5As and InP layers are optimized to provide low resistance for fast charge injection while maintaining high barrier height for long-term retention, resolving the DRAM storage time limitation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory cell enables rapid writing and reading with nanosecond access times while maintaining storage for several years, utilizing a semiconductor heterostructure with a space charge zone to securely store bit information with minimal charge carriers, enhancing durability and energy efficiency compared to traditional memory cells.
Implementation Method 1
The semiconductor heterostructure forms a potential well in which charge carriers can be trapped
Implementation Method 2
the space charge zone is extended to the semiconductor heterostructure for storage operation, ie. for the condition in which the storage charge is retained, so that the charge carriers trapped in the semiconductor heterostructure cannot escape from it
Data Source
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AI summary
The invention relates, among other things, to a memory cell (10) for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals (40, 130) and a semiconductor structure (11) with a band curve (EL) that has at least one potential well (200). The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure (80). The semiconductor heterostructure and the space charge region are spatially arranged relative to one another in such a way that the semiconductor heterostructure is located within the space charge region when the maintaining voltage is applied, at the edge of or outside the space charge region when the supply voltage is applied, and within the space charge region when the discharge voltage is applied.