Heterostructure Template Layer for III-V Semiconductor Lattice Mismatch
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Solution Overview
Problem
The growth of high-quality III-V compound semiconductor films on dissimilar substrates is challenging due to lattice constant and thermal expansion coefficient mismatches, which affects the performance of transistors like finFETs, as they require high electron or hole mobility for high drive currents.
Innovation Solution
The development of heterostructures involving a substrate with a crystalline template layer, a barrier layer, and a device layer, where the template layer absorbs lattice mismatch and the barrier layer has a higher bandgap energy to reduce leakage current, allowing for the formation of high mobility III-V compound semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If III-V compound semiconductor films are grown on dissimilar substrates, then high electron mobility is achieved, but lattice mismatch and thermal expansion coefficient differences cause misfit dislocations and reduce film quality
Solution Approach 1:
The patent introduces a substrate template layer as an intermediary between the dissimilar substrate and the III-V compound semiconductor film. This template layer has lattice constants and thermal expansion coefficients that are intermediate between those of the substrate and the III-V compound semiconductor, thereby reducing misfit dislocations and improving film quality while maintaining high electron mobility
Solution Approach 2:
The patent creates a composite heterostructure consisting of multiple layers including the substrate, substrate template layer, and III-V compound semiconductor film. Each layer is carefully selected with specific lattice constants and thermal expansion coefficients to form a graded transition that minimizes interface defects and maintains high film quality
2Manufacturing precision
If heterostructures are formed to reduce misfit dislocations, then film quality improves, but device complexity increases due to multiple layers
Solution Approach 1:
The patent segments the heterostructure into distinct functional layers: substrate, substrate template layer, and III-V compound semiconductor film. Each layer performs a specific function and can be independently optimized and processed, which simplifies the overall manufacturing process despite the multiple layers
3Ease of manufacture
If conventional substrates are used for III-V compound semiconductors, then processing is simplified, but thermal expansion coefficient mismatch causes misfit dislocations
Solution Approach 1:
The patent changes the thermal expansion coefficient parameter by introducing a substrate template layer with intermediate thermal expansion properties. This gradual transition in thermal expansion coefficients reduces thermal stress and misfit dislocations during temperature cycling, while the template layer can be grown using conventional processing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high mobility III-V compound semiconductor devices with reduced misfit dislocations and leakage current, enhancing the performance of transistors such as finFETs by achieving a dislocation-free heterostructure with low strain and simplified processing.
Implementation Method 1
the template layer absorbs lattice mismatch
Implementation Method 2
the barrier layer has a higher bandgap energy to reduce leakage current
Data Source
AI summary
Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.