Heterostructure Transistor Gate Separation for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current transistor scaling methods, such as silicon metal oxide semiconductor field effect transistors (Si MOSFETs), face limitations in achieving the 15 nm node due to issues like breakdown voltage, output conductance, and gate leakage current, particularly with gate scaling below 20 nm and oxide thickness under 5 nm.
Innovation Solution
A field-effect transistor device with a semiconductor heterostructure featuring a vertically stacked configuration and a semiconductor gate layer of less than 100 Angstroms thickness, separated by heterosteps instead of an oxide layer, allowing for improved control of current flow between source and drain layers, and a heterojunction bipolar transistor device that operates as a field-effect transistor by applying an input voltage to a base/gate terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate scaling is performed below 20 nm with oxide thickness under 5 nm, then transistor size is reduced, but gate leakage current increases due to tunneling through the thin gate oxide
Solution Approach 1:
The patent changes the gate oxide thickness parameter to an ultra-thin regime (less than 5 nm, preferably less than 3 nm), which enables tunneling-based switching operation. This parameter change allows the transistor to function at scaled dimensions while managing leakage through controlled tunneling rather than uncontrolled breakdown
Solution Approach 2:
The patent inverts the conventional approach by using tunneling (typically a leakage mechanism) as the primary switching mechanism. Instead of preventing tunneling, the device exploits quantum tunneling through the thin gate oxide to enable on/off control, transforming a harmful effect into a useful function
2Length of moving object
If gate oxide thickness is reduced under 5 nm, then transistor scaling is achieved, but breakdown voltage decreases
Solution Approach 1:
The patent employs multiple parameter changes including gate oxide thickness (less than 5 nm), gate length (less than 20 nm), and channel width ratios to achieve scaling while managing breakdown characteristics. The specific combination of these parameters allows the device to operate at scaled dimensions with controlled breakdown behavior
Solution Approach 2:
The patent introduces dynamic control through the thin gate oxide, where the gate voltage can dynamically modulate the tunneling current. This dynamic operation allows the device to switch between low-leakage off-state and high-current on-state, effectively managing voltage breakdown through active control rather than passive structural constraints
3Ease of manufacture
If conventional Si MOSFET scaling methods are used, then manufacturing process is maintained, but the 15 nm node requirements are not met
Solution Approach 1:
The patent employs a composite structure combining silicon channel with high-k dielectric gate oxide materials. This composite approach allows the device to achieve the required electrical performance at 15 nm node while maintaining compatibility with existing silicon-based manufacturing processes. The high-k material provides equivalent oxide thickness with greater physical thickness, reducing leakage while maintaining capacitance
Data Source
AI summary
A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages.