HetIRS Reed-Solomon Decoding for DRAM Erasure Correction
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Solution Overview
Problem
Existing memory devices face challenges in efficiently correcting errors due to single device failures or single read access failures, which conventional ECC techniques struggle to address, leading to uncorrectable errors and increased costs from additional parity bit requirements.
Innovation Solution
Implementing a heterogeneous interleaved Reed-Solomon (HetIRS) decoding technique that divides a single codeword into two sub-codewords, leveraging erasure decoding to correct errors by identifying faulty DRAM components, reducing the need for excessive parity symbols and improving decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC techniques are used to correct errors due to single device failures, then reliability is improved, but the number of parity bits required increases significantly
Solution Approach 1:
The patent divides a single codeword into two sub-codewords, where each sub-codeword contains a portion of the data symbols and parity symbols. This segmentation allows the system to achieve the same error correction capability with fewer total parity bits by distributing the correction burden across both sub-codewords and utilizing erasure decoding when device failures are detected
Solution Approach 2:
The patent changes the decoding approach by implementing erasure decoding, which assumes that error locations are known (erased) and only requires correction of error magnitudes. This parameter change in the decoding strategy reduces the number of parity bits needed compared to conventional error correction that must locate and correct all errors without prior knowledge of error positions
2Quantity of substance
If conventional ECC techniques cannot detect and correct entire device failures, then parity bit requirements are reduced, but uncorrectable errors increase
Solution Approach 1:
The patent performs preliminary detection of device failures before attempting full error correction. By first identifying which devices have failed (creating erasures), the system can then apply targeted erasure decoding to those specific locations, ensuring that device failures are corrected while using fewer parity bits than conventional methods
3Productivity
If heterogeneous interleaved Reed-Solomon decoding with erasure decoding is implemented, then decoding efficiency is improved, but system complexity increases
Solution Approach 1:
The patent segments the decoding process into distinct phases: first detecting device failures to identify erasure locations, then applying erasure decoding to correct errors at those locations. This segmentation of the decoding process improves efficiency by avoiding unnecessary computation on non-erased symbols, while the modular structure helps manage system complexity
Data Source
AI summary
Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.