Heuristic Input Vector Generation for Leakage Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for reducing leakage current in integrated circuits require manual determination of input vectors or probabilistic analysis, which are inefficient and not optimized for minimizing power consumption and heat dissipation.
Innovation Solution
A method using greedy heuristics with output terminal biased off-state stacking device to generate an input vector by transforming integrated circuits into weighted graphs, selecting the deepest serial stack, and assigning weights in a descending order to minimize leakage current, applicable in algorithms like branch-and-bound or simulated annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If manual determination of input vectors is used to reduce leakage current, then leakage current reduction is achieved, but the process efficiency and automation level deteriorate
Solution Approach 1:
The system automatically generates input vectors for leakage current reduction without requiring manual visual inspection. The automated algorithm transforms the logic circuit into a graph representation, computes optimal input vectors based on off-state device stacking depth, and applies them to minimize leakage current, enabling the system to serve itself rather than requiring human intervention
Solution Approach 2:
The manual visual inspection process is replaced with an automated computational algorithm. The system uses graph transformation and algorithmic computation to determine optimal input vectors, substituting the mechanical/manual process with an automated electronic computing approach that efficiently minimizes leakage current
2Extent of automation
If probabilistic analysis algorithm is used to compute input vector, then automation is improved, but the optimization precision for leakage current reduction deteriorates
Solution Approach 1:
The approach changes from probabilistic analysis to a deterministic parameter-based optimization. The system transforms the logic circuit into a graph representation and uses the depth of off-state device stacking as a key parameter to determine optimal input vectors. This parameter-driven approach provides more precise and reliable leakage current reduction compared to probabilistic methods
Solution Approach 2:
The system performs preliminary transformation of the logic circuit into a graph representation before computing input vectors. By pre-processing the circuit structure and identifying off-state device stacking relationships in advance, the system can more effectively determine optimal input vectors that minimize leakage current, rather than relying on probabilistic computation during operation
Data Source
AI summary
A method for generating an input vector to reduce the leakage current in an integrated circuit by using heuristics includes transforming the integrated circuit to a logic representation with PMOS and NMOS parts and P and N devices of the integrated circuit into edges, selecting between PMOS and NMOS logic representations the one with deepest serial stack; and for the selected PMOS or NMOS logic representation, assigning weights to the edges, thereby generating a weighted graph. The assignment includes starting from the output terminal to the Power Vdd (for PMOS) or Ground Vss (for NMOS), and labeling edge weights in a descending order. The resulted cost function from the method of the present invention can be applied as heuristics in different algorithms, such as branch-and-bound, simulated annealing, or genetic algorithm.