Block Mapping in HEVC Encoders Using Map Arrays
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Solution Overview
Problem
High Efficiency Video Coding (HEVC) decoders and encoders face challenges in efficiently managing and accessing large amounts of data for rectangular blocks of varying sizes, specifically Transform Units and Coding Units, which hinders data transmission and processing efficiency.
Innovation Solution
A method and architecture that utilize a parallel processing unit with software-configurable general-purpose processors and globally-shared memory to efficiently store and access block data, allowing for fast access and parallel processing by organizing data into contiguous arrays with a map array that describes block positions, reducing memory usage and transmission time between central and parallel processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If all block data is stored at the resolution of the minimum coding unit, then complete data coverage is achieved, but memory usage increases significantly
Solution Approach 1:
The patent creates a simplified map array that copies only the essential positional information of blocks rather than storing complete block data at minimum coding unit resolution. This map serves as a representative copy that enables data location without requiring full-resolution storage, thereby reducing memory usage while maintaining data accessibility.
Solution Approach 2:
The patent extracts only the critical positional metadata from the full block data and stores it in a separate map array. This extraction allows the system to maintain complete data coverage capability while using significantly less memory for the map structure, as only coordinates and block identifiers are stored rather than complete pixel data.
2Loss of time
If block data is accessed by searching directly in block arrays, then data can be located, but time consumption increases
Solution Approach 1:
The patent pre-organizes block positional information in a map array during an initial setup phase, creating an indexed structure that maps block identifiers to their coordinates. This preliminary organization enables O(1) or O(log n) data location time during subsequent operations, compared to O(n) linear search time in unorganized block arrays.
Solution Approach 2:
The patent introduces a map array as an intermediary data structure between the block arrays and the data access operations. This intermediary layer provides efficient lookup capabilities by storing pre-computed positional information, eliminating the need for direct searching in the block arrays and simplifying the data access operation.
3Productivity
If neighbor data dependencies between blocks are maintained, then data accuracy is preserved, but processing serialization occurs
Solution Approach 1:
The patent segments the processing workflow into distinct phases: map construction (which establishes all positional relationships) and data processing (which uses the pre-established map). This segmentation allows the data processing phase to operate in parallel without neighbor data dependencies, as all spatial relationships are pre-determined in the map structure, while still maintaining data accuracy through the preserved positional information.
4Loss of time
If data transmission between CPU and PPU is performed with large data sets, then complete data is transferred, but transmission time increases
Solution Approach 1:
The patent transfers only the compact map array from CPU to PPU rather than transferring large sets of complete block data. The map array serves as a lightweight copy containing only positional metadata, which is sufficient for the PPU to locate and process block data efficiently. This dramatically reduces the volume of data transmitted while maintaining the ability to access complete data when needed.
Data Source
AI summary
An apparatus includes a central processing unit and a parallel processing unit. The parallel processing unit includes an array of software-configurable general purpose processors, a globally-shared memory, and a shared memory. Each of the software-configurable general purpose processors in the array of software-configurable general purpose processors has access to the globally-shared memory to execute one or more portions of at least one of (i) a decoding program, (ii) an encoding program, and (iii) an encoding and decoding program. The shared memory is accessible by the central processing unit to program the shared memory with a map array describing a position of block data in one or more associated arrays.