Combined HEVC Deblocking and SAO Filter Pipeline
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Solution Overview
Problem
The HEVC video coding standard's sequential application of deblocking and sample-adaptive offset filters leads to increased processing time and silicon chip area usage, as the SAO filter must wait for the deblocking filter to complete, resulting in inefficiencies and higher costs for implementing loop filters.
Innovation Solution
Combining the deblocking filter and SAO filter into a single decoder pipeline stage without intermediate buffering, allowing for almost entirely parallel processing of pixels, which reduces the need for additional memory and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the deblocking filter and SAO filter are applied sequentially in separate decoder pipeline stages, then the filtering can be performed in a structured manner, but the processing time increases and silicon chip area usage increases
Solution Approach 1:
The patent combines the deblocking filter and SAO filter into a single decoder pipeline stage, eliminating the sequential processing requirement. The combined filter processes pixels through both deblocking and SAO operations in parallel, reducing processing time while maintaining filtering quality.
Solution Approach 2:
The combined filter is divided into multiple processing units that can operate in parallel. The filter includes a first processing unit for deblocking operations and a second processing unit for SAO operations, which can process different pixels simultaneously, enabling parallel processing while reducing overall processing time.
2Reliability
If the deblocking filter and SAO filter are applied sequentially in separate decoder pipeline stages, then the filtering can be performed in a structured manner, but the silicon chip area required increases
Solution Approach 1:
The patent merges the deblocking filter and SAO filter into a single integrated filter structure, eliminating the need for separate filter implementations. This consolidation reduces the silicon chip area required while maintaining the functional capabilities of both filters.
Solution Approach 2:
The combined filter is designed to perform multiple functions (deblocking and SAO filtering) within a single pipeline stage. The filter structure includes shared resources and unified processing architecture that reduce the overall area requirement compared to implementing separate filters.
3Reliability
If the SAO filter waits for the deblocking filter to complete, then the processing can be performed sequentially with clear dependencies, but the productivity decreases
Solution Approach 1:
The filter is segmented into multiple independent processing units that can operate in parallel. The first processing unit handles deblocking operations while the second processing unit handles SAO operations on different pixel data, eliminating the sequential dependency and improving decoding speed while maintaining processing correctness.
Solution Approach 2:
The patent implements preliminary buffering of pixel data to enable the SAO filter to process pixels as soon as they are available from the deblocking filter, without waiting for the entire deblocking process to complete. This preliminary action allows overlapping operations and improves productivity.
Data Source
AI summary
Systems and methods are provided that allow a deblocking filter and a sample adaptive offset (SAO) filter to be combined in a loop filter stage of a High Efficiency Video Coding (HEVC) decoder. In combining the deblocking filter and the SAO filter, an intermediate buffer may not be utilized, while still allowing for the deblocking filter and the SAO filter to operate substantially in parallel. The order of pixel processing and the parallelization of operation is such that the processing performed by the SAO filter need not hinder the processing performed by the deblocking filter within the loop filter stage. Additionally, and by combining the deblocking filter and the SAO filter without utilizing buffering therebetween, savings in space and cost in implementing the HEVC decoder may be realized.