3D Memory Gate Stack with Hexagonal Cell Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing three-dimensional nonvolatile memory devices face challenges in improving operational reliability and manufacturing yield due to limitations in cell integration and structural complexity, particularly in forming stable and efficient gate stack structures.
Innovation Solution
A memory device with a gate stack structure comprising cylindrical first cell plugs and hexagonal prism second cell plugs, along with a manufacturing method involving sacrificial layers and interlayer insulating layers, is developed. This method includes forming first cell plugs, creating holes for second cell plugs, and filling conductive layers to form plate electrodes, enhancing integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional single-layer memory cell structure is used, then manufacturing process is simpler, but degree of integration is limited
Solution Approach 1:
The patent transitions from a traditional planar single-layer memory structure to a three-dimensional stacked structure with multiple layers of memory cells vertically arranged. This dimensional change allows significantly higher integration density without proportionally increasing manufacturing complexity, as the basic cell structure remains similar across layers
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells, interlayer insulating layers, and gate electrodes. This segmentation into repeatable modular units enables systematic scaling of integration capacity while maintaining manageable manufacturing processes for each layer
2Quantity of substance
If three-dimensional stacked structure is implemented, then degree of integration is improved, but manufacturing complexity increases
Solution Approach 1:
The gate electrodes serve multiple functions: they act as control gates for memory cells in their own layer, as interlayer insulating barriers between layers, and as structural support elements. This multi-functionality reduces the need for additional dedicated components, thereby managing complexity despite the three-dimensional architecture
Solution Approach 2:
The structure employs nested arrangements where channel layers are positioned within gate electrode structures, memory cells are nested within the stacked layers, and interlayer insulating layers are integrated between functional layers. This nesting consolidates multiple functions into overlapping spatial arrangements, reducing overall structural complexity
3Ease of manufacture
If conventional cell plug formation method is used, then manufacturing process is simpler, but operational reliability is limited
Solution Approach 1:
Different regions of the memory device employ different cell plug structures optimized for their specific functions: cylindrical cell plugs in certain regions provide stable electrical characteristics, while hexagonal prism cell plugs in other regions enhance structural stability and alignment. This local optimization of structure quality improves operational reliability without requiring complete process redesign
Solution Approach 2:
The patent varies geometric parameters of cell plugs (cylindrical vs. hexagonal prism shapes, different dimensions) to optimize performance characteristics. These parameter changes enable improved operational reliability through better electrical stability and structural integrity while maintaining compatibility with existing manufacturing processes
Data Source
AI summary
There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a peripheral circuit disposed on a substrate; and a gate stack structure overlapping with the peripheral circuit. The gate stack structure includes a plurality of first cell plugs having substantially a cylindrical structure and a plurality of second cell plugs having substantially a hexagonal prism structure.