Hexagonal Pillar Arrangement in 3D NAND Memory
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Solution Overview
Problem
Current three-dimensional NAND memory architectures face challenges in optimizing memory access time and density due to limitations in pillar arrangements, which affect data manipulation speed and storage efficiency.
Innovation Solution
A shifted pillar arrangement is introduced, where pillars are disposed in a hexagonal pattern with specific spacing and offsetting relative to bitlines, allowing for increased bitline allocation and reduced bitline pitch, resulting in a denser memory array with improved data access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional pillar arrangements are used in 3D NAND memory, then the memory array can be fabricated with standard configurations, but the memory access time is increased and data manipulation speed is reduced
Solution Approach 1:
The patent applies asymmetry by shifting the pillar arrangement relative to the bitlines, creating an asymmetric configuration where pillars are offset from their traditional aligned positions. This asymmetric positioning optimizes the coupling between bitlines and memory cells, enabling faster data access and manipulation while reducing memory access time.
Solution Approach 2:
The patent introduces a shifted pillar arrangement that effectively utilizes spatial dimensions differently from traditional configurations. By offsetting pillars in the lateral dimension relative to bitlines, the design creates more efficient data paths and reduces access time without increasing vertical stacking complexity.
2Quantity of substance
If pillar density is increased to improve storage capacity, then memory density improves, but bitline pitch reduction becomes difficult and manufacturing complexity increases
Solution Approach 1:
The asymmetric shifted pillar arrangement allows for optimized bitline pitch by breaking the symmetry of traditional grid-based layouts. This enables tighter spacing between bitlines while maintaining manufacturability, as the shifted configuration creates more favorable routing patterns and reduces interference between adjacent bitlines.
Solution Approach 2:
The patent changes the spatial parameters of the pillar arrangement by introducing a systematic shift offset. This parameter change optimizes the geometric relationship between pillars and bitlines, enabling higher memory density through reduced bitline pitch without proportionally increasing manufacturing complexity.
3Quantity of substance
If more bitlines are allocated to increase memory capacity, then storage capacity improves, but the number of pages per block increases and copy time increases
Solution Approach 1:
The shifted pillar arrangement creates an asymmetric mapping between bitlines and memory pages, allowing for optimized page organization. This asymmetric configuration enables more efficient data grouping and access patterns, reducing the effective number of pages that need to be copied during block operations while maintaining high storage capacity.
Data Source
AI summary
Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.