Modified Hexagonal Pillar Packing for Vertical NAND Memory Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In vertical NAND memory architectures, the existing data line and select gate arrangements face challenges in efficiently managing the complex interconnections and packing densities of vertically-stacked memory cells, leading to limitations in data storage capacity and operational efficiency.
Innovation Solution
The implementation of a modified hexagonal packing arrangement for semiconductor pillars, where each pillar is surrounded by gate dielectric material and electrically coupled to data lines and drain-side select gates, allowing for optimized electrical coupling and increased packing density without compromising operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional data line arrangement is used in vertical NAND memory, then the interconnection structure is simpler to manufacture, but the packing density of memory cells is reduced
Solution Approach 1:
The patent transitions from planar data line arrangements to a three-dimensional configuration where data lines are positioned at multiple vertical levels relative to the stacked memory cells. This dimensional change allows data lines to access memory cells from different heights, increasing packing density without proportionally increasing interconnection complexity.
Solution Approach 2:
The patent implements a nested arrangement where data lines are positioned within and around the vertical stack of memory cells. The data lines are integrated into the three-dimensional structure, with some lines positioned laterally and others vertically, creating a compact nested configuration that maximizes space utilization.
2Reliability
If data lines are positioned far from pillars, then manufacturing is easier, but electrical coupling efficiency deteriorates
Solution Approach 1:
The patent implements different data line positioning strategies for different regions of the memory array. Data lines are positioned at optimized distances from pillars depending on the local electrical coupling requirements, allowing closer positioning where high coupling efficiency is critical while maintaining manufacturability in other regions.
Solution Approach 2:
The patent varies the distance parameter between data lines and pillars based on operational requirements. By adjusting this critical dimension parameter locally, the design achieves optimal electrical coupling efficiency while remaining within manufacturing process capabilities and tolerances.
Data Source
AI summary
Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.