Hexagonal Source/Drain Epitaxy for Contact Resistance and Uniformity
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Solution Overview
Problem
As IC feature sizes shrink, high contact resistances between source/drain features and local contacts increase, negating performance gains and leading to reduced uniformity control and reliability due to smaller contact surface areas, which existing approaches attempt to address by increasing source/drain feature size but at the cost of compromised uniformity.
Innovation Solution
The method involves engineering the profiles of source/drain features through epitaxial growth processes to increase contact surface area without losing uniformity control, using techniques like cyclic deposition/etch processes and selective epitaxial growth to form source/drain features with specific morphologies that reduce contact resistances and improve critical dimension uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain feature size is increased to reduce contact resistance, then contact resistance decreases, but uniformity control of critical dimensions deteriorates
Solution Approach 1:
The patent transitions from planar source/drain features to three-dimensional FinFET structures with vertically extending fins. This dimensional change increases the contact surface area between source/drain regions and local contacts through the vertical fin surfaces, thereby reducing contact resistance without requiring lateral expansion that would compromise uniformity control of critical dimensions.
Solution Approach 2:
The patent modifies the geometric parameters of source/drain features by creating tapered fin structures with controlled aspect ratios. By adjusting the fin height, width, and taper angle through epitaxial growth processes, the contact surface area is optimized to reduce contact resistance while maintaining precise control over critical dimensions through parameter optimization.
2Productivity
If IC feature size is reduced to improve production efficiency, then production efficiency increases, but contact surface area decreases leading to higher contact resistance
Solution Approach 1:
The patent resolves the conflict between reduced feature size for higher productivity and reduced contact surface area by moving to three-dimensional FinFET structures. The vertical fin surfaces provide additional contact area in the vertical dimension, compensating for the reduced lateral dimensions while maintaining high production efficiency through scalable fabrication processes.
Solution Approach 2:
The patent employs composite material structures with different semiconductor materials (e.g., SiGe source/drain regions with silicon channel) to optimize both the contact properties and the electrical characteristics. This material composition enables reduced contact resistance in scaled devices while maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the contact surface area between source/drain features and local contacts, reducing contact resistances and enhancing overall device performance while maintaining uniformity control over critical dimensions.
Implementation Method 1
forming a first source/drain layer over the active region in the source/drain trenches from a first precursor; forming a second source/drain layer over the first source/drain layer from a second precursor
Implementation Method 2
forming a first source/drain layer over the active region in the source/drain trenches from a first precursor; forming a second source/drain layer over the first source/drain layer from a second precursor
Data Source
AI summary
In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.