Hexagonal Trench MOSFET Layout for Lower Wafer Warpage
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Solution Overview
Problem
Wafer warpage issues in shielded gate trench (SGT) MOSFETs, particularly due to increasing trench depth and field oxide thickness, lead to manufacturing challenges and errors in vacuum absorption and transportation, especially in medium and high voltage applications.
Innovation Solution
A novel SGT MOSFET design featuring hexagonal deep trenches and multiple stepped epitaxial layers to reduce wafer warpage and improve DC and AC performance, with a substrate of a first conductivity type, epitaxial layers, and specific insulating films to balance oxide charge and reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench depth is increased to achieve higher breakdown voltage, then device voltage capability is improved, but wafer warpage increases making manufacturing difficult
Solution Approach 1:
The patent divides the single deep trench structure into multiple shallower trenches arranged in a hexagonal pattern. Each trench has a depth of 5-15 micrometers, collectively achieving the voltage blocking capability of a single deep trench while reducing individual trench stress and wafer warpage
Solution Approach 2:
The patent transitions from a conventional linear or rectangular trench arrangement to a hexagonal geometric configuration. This dimensional reorganization optimizes space utilization, ensures uniform stress distribution in all directions, and reduces overall wafer warpage while maintaining effective voltage blocking
2Reliability
If field oxide thickness is increased to achieve higher breakdown voltage, then device voltage capability is improved, but wafer warpage increases causing manufacturing errors
Solution Approach 1:
The patent replaces a single thick field oxide layer with multiple thinner field oxide layers (500-2000 nanometers each) positioned between adjacent trenches. This segmentation achieves equivalent electrical isolation and voltage blocking while reducing the cumulative stress and warpage caused by thick oxide layers
Solution Approach 2:
The patent introduces a multi-layered field oxide structure with vertical stacking of thinner oxide layers, replacing the conventional single thick horizontal oxide layer. This dimensional change maintains electrical performance while reducing wafer warpage
3Reliability
If gate trench length is increased to improve device performance, then specific on-resistance is reduced, but wafer warpage increases beyond critical values
Solution Approach 1:
The patent divides the gate function across multiple shorter trenches arranged hexagonally around a central region. Each trench has a reduced length compared to a single long gate trench, but the collective arrangement achieves equivalent or improved on-resistance while reducing the warpage induced by long trench structures
Solution Approach 2:
The patent reorganizes the gate structure from a linear extended trench to a hexagonal radial arrangement. This geometric transformation reduces the maximum trench length in any single direction while maintaining effective gate control across the device area, thereby reducing wafer warpage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hexagonal trench layout and multiple epitaxial layers effectively reduce wafer warpage and enhance performance by ensuring uniform mesa widths and stress reduction, improving the device's ruggedness and efficiency in medium and high voltage ranges.
Implementation Method 1
an epitaxial layer of the first conductivity type grown on the substrate
Data Source
AI summary
A shielded gate trench (SGT) MOSFET structure with a hexagonal deep trench layout and multiple epitaxial layers for wafer warpage and on-resistance reductions is disclosed, wherein a gate electrode surrounds the deep trench in each unit cell as a closed cell. A source-body contact is disposed between the gate electrode and the deep trench. Moreover, the gate electrode is planar, or vertically formed in an upper portion of a gate trench in each unit cell.