Hexagonal Trench Transistor for Short Channel Effect Suppression
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Solution Overview
Problem
The short channel effect in MOS transistors, characterized by an undesirable increase in threshold voltage as channel length is reduced, degrades device characteristics and hinders the production of consistent threshold voltages, posing a challenge for high-density IC circuits.
Innovation Solution
A transistor structure is fabricated using a substrate with a doped well and a gate structure, featuring hexagonal-shaped trenches filled with epitaxial layers of different conductive types, where a first epitaxial layer surrounds a second epitaxial layer serving as the source/drain region, effectively preventing the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length in MOS transistors is reduced to increase speed, then the operating speed is improved, but the threshold voltage increases due to the short channel effect
Solution Approach 1:
The patent applies local quality by creating a hexagonal-shaped trench with specific geometric characteristics (side length 5-15 nm, depth 10-30 nm) at a localized position adjacent to the gate structure. This localized structural modification creates a specific electric field distribution in the short channel region, which compensates for the threshold voltage increase caused by short channel effects while maintaining the reduced channel length for high-speed operation.
Solution Approach 2:
The patent changes the geometric parameters of the trench structure (hexagonal shape, specific side length range of 5-15 nm, depth range of 10-30 nm) to optimize the electric field distribution. By adjusting these parameters, the invention achieves effective suppression of short channel effects and maintains consistent threshold voltages while operating at reduced channel lengths for high-speed performance.
2Productivity
If the channel length is reduced to increase density, then the IC circuit density is improved, but the short channel effect degrades device characteristics
Solution Approach 1:
The hexagonal-shaped trench structure is implemented as a localized modification in the semiconductor device architecture. By positioning this specific geometric structure (with side length 5-15 nm and depth 10-30 nm) adjacent to the gate structure, the patent creates a localized electric field that counteracts short channel effects, enabling high-density integration while maintaining reliable device characteristics.
Solution Approach 2:
The patent employs a composite structure combining the hexagonal-shaped trench with the surrounding semiconductor materials. This composite architecture, featuring specific geometric parameters (hexagonal cross-section, controlled dimensions), creates a unique electric field distribution that suppresses short channel effects and maintains device reliability in high-density IC circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent threshold voltages and prevents the short channel effect, addressing the limitations of conventional methods by using epitaxial layers to manage dopant concentrations and stresses, thereby enhancing transistor performance.
Implementation Method 1
a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench
Data Source
AI summary
A fabricating method of a transistor structure includes providing a substrate with a doped well disposed within the substrate. Later, a gate structure is formed to be disposed on the doped well. Next, a hexagonal-shaped trench is formed to be embedded in the doped well at one side of the gate structure. Subsequently, a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench, wherein the first epitaxial layer surrounds the second epitaxial layer, the second epitaxial layer serves as a source/drain doped region of the transistor structure, and the first-type dopants and the second-type dopants are different conductive types.